| 641 | extern int elf32_nxstack; |
| 642 | |
| 643 | void |
| 644 | initializecpu(void) |
| 645 | { |
| 646 | uint64_t msr; |
| 647 | |
| 648 | switch (cpu) { |
| 649 | #ifdef I486_CPU |
| 650 | case CPU_BLUE: |
| 651 | init_bluelightning(); |
| 652 | break; |
| 653 | case CPU_486DLC: |
| 654 | init_486dlc(); |
| 655 | break; |
| 656 | case CPU_CY486DX: |
| 657 | init_cy486dx(); |
| 658 | break; |
| 659 | case CPU_M1SC: |
| 660 | init_5x86(); |
| 661 | break; |
| 662 | #ifdef CPU_I486_ON_386 |
| 663 | case CPU_486: |
| 664 | init_i486_on_386(); |
| 665 | break; |
| 666 | #endif |
| 667 | case CPU_M1: |
| 668 | init_6x86(); |
| 669 | break; |
| 670 | #endif /* I486_CPU */ |
| 671 | #ifdef I586_CPU |
| 672 | case CPU_586: |
| 673 | switch (cpu_vendor_id) { |
| 674 | case CPU_VENDOR_AMD: |
| 675 | #ifdef CPU_WT_ALLOC |
| 676 | if (((cpu_id & 0x0f0) > 0) && |
| 677 | ((cpu_id & 0x0f0) < 0x60) && |
| 678 | ((cpu_id & 0x00f) > 3)) |
| 679 | enable_K5_wt_alloc(); |
| 680 | else if (((cpu_id & 0x0f0) > 0x80) || |
| 681 | (((cpu_id & 0x0f0) == 0x80) && |
| 682 | (cpu_id & 0x00f) > 0x07)) |
| 683 | enable_K6_2_wt_alloc(); |
| 684 | else if ((cpu_id & 0x0f0) > 0x50) |
| 685 | enable_K6_wt_alloc(); |
| 686 | #endif |
| 687 | if ((cpu_id & 0xf0) == 0xa0) |
| 688 | /* |
| 689 | * Make sure the TSC runs through |
| 690 | * suspension, otherwise we can't use |
| 691 | * it as timecounter |
| 692 | */ |
| 693 | wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); |
| 694 | break; |
| 695 | case CPU_VENDOR_CENTAUR: |
| 696 | init_winchip(); |
| 697 | break; |
| 698 | case CPU_VENDOR_TRANSMETA: |
| 699 | init_transmeta(); |
| 700 | break; |
no test coverage detected