| 901 | } |
| 902 | |
| 903 | static void |
| 904 | enable_K6_2_wt_alloc(void) |
| 905 | { |
| 906 | quad_t size; |
| 907 | u_int64_t whcr; |
| 908 | register_t saveintr; |
| 909 | |
| 910 | saveintr = intr_disable(); |
| 911 | wbinvd(); |
| 912 | |
| 913 | #ifdef CPU_DISABLE_CACHE |
| 914 | /* |
| 915 | * Certain K6-2 box becomes unstable when write allocation is |
| 916 | * enabled. |
| 917 | */ |
| 918 | /* |
| 919 | * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), |
| 920 | * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported. |
| 921 | * All other bits in TR12 have no effect on the processer's operation. |
| 922 | * The I/O Trap Restart function (bit 9 of TR12) is always enabled |
| 923 | * on the AMD-K6. |
| 924 | */ |
| 925 | wrmsr(0x0000000e, (u_int64_t)0x0008); |
| 926 | #endif |
| 927 | /* Don't assume that memory size is aligned with 4M. */ |
| 928 | if (Maxmem > 0) |
| 929 | size = ((Maxmem >> 8) + 3) >> 2; |
| 930 | else |
| 931 | size = 0; |
| 932 | |
| 933 | /* Limit is 4092M bytes. */ |
| 934 | if (size > 0x3fff) |
| 935 | size = 0x3ff; |
| 936 | whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22); |
| 937 | |
| 938 | #if defined(NO_MEMORY_HOLE) |
| 939 | if (whcr & (0x3ffLL << 22)) |
| 940 | whcr |= 1LL << 16; |
| 941 | #else |
| 942 | /* |
| 943 | * There is no way to know wheter 15-16M hole exists or not. |
| 944 | * Therefore, we disable write allocate for this range. |
| 945 | */ |
| 946 | whcr &= ~(1LL << 16); |
| 947 | #endif |
| 948 | wrmsr(0x0c0000082, whcr); |
| 949 | |
| 950 | intr_restore(saveintr); |
| 951 | } |
| 952 | #endif /* I585_CPU && CPU_WT_ALLOC */ |
| 953 | |
| 954 | #include "opt_ddb.h" |
no test coverage detected