| 851 | } |
| 852 | |
| 853 | static void |
| 854 | enable_K6_wt_alloc(void) |
| 855 | { |
| 856 | quad_t size; |
| 857 | u_int64_t whcr; |
| 858 | register_t saveintr; |
| 859 | |
| 860 | saveintr = intr_disable(); |
| 861 | wbinvd(); |
| 862 | |
| 863 | #ifdef CPU_DISABLE_CACHE |
| 864 | /* |
| 865 | * Certain K6-2 box becomes unstable when write allocation is |
| 866 | * enabled. |
| 867 | */ |
| 868 | /* |
| 869 | * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), |
| 870 | * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported. |
| 871 | * All other bits in TR12 have no effect on the processer's operation. |
| 872 | * The I/O Trap Restart function (bit 9 of TR12) is always enabled |
| 873 | * on the AMD-K6. |
| 874 | */ |
| 875 | wrmsr(0x0000000e, (u_int64_t)0x0008); |
| 876 | #endif |
| 877 | /* Don't assume that memory size is aligned with 4M. */ |
| 878 | if (Maxmem > 0) |
| 879 | size = ((Maxmem >> 8) + 3) >> 2; |
| 880 | else |
| 881 | size = 0; |
| 882 | |
| 883 | /* Limit is 508M bytes. */ |
| 884 | if (size > 0x7f) |
| 885 | size = 0x7f; |
| 886 | whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1); |
| 887 | |
| 888 | #if defined(NO_MEMORY_HOLE) |
| 889 | if (whcr & (0x7fLL << 1)) |
| 890 | whcr |= 0x0001LL; |
| 891 | #else |
| 892 | /* |
| 893 | * There is no way to know wheter 15-16M hole exists or not. |
| 894 | * Therefore, we disable write allocate for this range. |
| 895 | */ |
| 896 | whcr &= ~0x0001LL; |
| 897 | #endif |
| 898 | wrmsr(0x0c0000082, whcr); |
| 899 | |
| 900 | intr_restore(saveintr); |
| 901 | } |
| 902 | |
| 903 | static void |
| 904 | enable_K6_2_wt_alloc(void) |
no test coverage detected