* Cyrix 486SLC/DLC/SR/DR series */
| 119 | * Cyrix 486SLC/DLC/SR/DR series |
| 120 | */ |
| 121 | static void |
| 122 | init_486dlc(void) |
| 123 | { |
| 124 | register_t saveintr; |
| 125 | u_char ccr0; |
| 126 | |
| 127 | saveintr = intr_disable(); |
| 128 | invd(); |
| 129 | |
| 130 | ccr0 = read_cyrix_reg(CCR0); |
| 131 | #ifndef CYRIX_CACHE_WORKS |
| 132 | ccr0 |= CCR0_NC1 | CCR0_BARB; |
| 133 | write_cyrix_reg(CCR0, ccr0); |
| 134 | invd(); |
| 135 | #else |
| 136 | ccr0 &= ~CCR0_NC0; |
| 137 | #ifndef CYRIX_CACHE_REALLY_WORKS |
| 138 | ccr0 |= CCR0_NC1 | CCR0_BARB; |
| 139 | #else |
| 140 | ccr0 |= CCR0_NC1; |
| 141 | #endif |
| 142 | #ifdef CPU_DIRECT_MAPPED_CACHE |
| 143 | ccr0 |= CCR0_CO; /* Direct mapped mode. */ |
| 144 | #endif |
| 145 | write_cyrix_reg(CCR0, ccr0); |
| 146 | |
| 147 | /* Clear non-cacheable region. */ |
| 148 | write_cyrix_reg(NCR1+2, NCR_SIZE_0K); |
| 149 | write_cyrix_reg(NCR2+2, NCR_SIZE_0K); |
| 150 | write_cyrix_reg(NCR3+2, NCR_SIZE_0K); |
| 151 | write_cyrix_reg(NCR4+2, NCR_SIZE_0K); |
| 152 | |
| 153 | write_cyrix_reg(0, 0); /* dummy write */ |
| 154 | |
| 155 | /* Enable caching in CR0. */ |
| 156 | load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ |
| 157 | invd(); |
| 158 | #endif /* !CYRIX_CACHE_WORKS */ |
| 159 | intr_restore(saveintr); |
| 160 | } |
| 161 | |
| 162 | /* |
| 163 | * Cyrix 486S/DX series |
no test coverage detected