* IBM Blue Lightning */
| 87 | * IBM Blue Lightning |
| 88 | */ |
| 89 | static void |
| 90 | init_bluelightning(void) |
| 91 | { |
| 92 | register_t saveintr; |
| 93 | |
| 94 | saveintr = intr_disable(); |
| 95 | |
| 96 | load_cr0(rcr0() | CR0_CD | CR0_NW); |
| 97 | invd(); |
| 98 | |
| 99 | #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE |
| 100 | wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ |
| 101 | #else |
| 102 | wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ |
| 103 | #endif |
| 104 | /* Enables 13MB and 0-640KB cache. */ |
| 105 | wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); |
| 106 | #ifdef CPU_BLUELIGHTNING_3X |
| 107 | wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ |
| 108 | #else |
| 109 | wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ |
| 110 | #endif |
| 111 | |
| 112 | /* Enable caching in CR0. */ |
| 113 | load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ |
| 114 | invd(); |
| 115 | intr_restore(saveintr); |
| 116 | } |
| 117 | |
| 118 | /* |
| 119 | * Cyrix 486SLC/DLC/SR/DR series |
no test coverage detected