* Enable write allocate feature of AMD processors. * Following two functions require the Maxmem variable being set. */
| 811 | * Following two functions require the Maxmem variable being set. |
| 812 | */ |
| 813 | static void |
| 814 | enable_K5_wt_alloc(void) |
| 815 | { |
| 816 | u_int64_t msr; |
| 817 | register_t saveintr; |
| 818 | |
| 819 | /* |
| 820 | * Write allocate is supported only on models 1, 2, and 3, with |
| 821 | * a stepping of 4 or greater. |
| 822 | */ |
| 823 | if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) { |
| 824 | saveintr = intr_disable(); |
| 825 | msr = rdmsr(0x83); /* HWCR */ |
| 826 | wrmsr(0x83, msr & !(0x10)); |
| 827 | |
| 828 | /* |
| 829 | * We have to tell the chip where the top of memory is, |
| 830 | * since video cards could have frame bufferes there, |
| 831 | * memory-mapped I/O could be there, etc. |
| 832 | */ |
| 833 | if(Maxmem > 0) |
| 834 | msr = Maxmem / 16; |
| 835 | else |
| 836 | msr = 0; |
| 837 | msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; |
| 838 | |
| 839 | /* |
| 840 | * There is no way to know wheter 15-16M hole exists or not. |
| 841 | * Therefore, we disable write allocate for this range. |
| 842 | */ |
| 843 | wrmsr(0x86, 0x0ff00f0); |
| 844 | msr |= AMD_WT_ALLOC_PRE; |
| 845 | wrmsr(0x85, msr); |
| 846 | |
| 847 | msr=rdmsr(0x83); |
| 848 | wrmsr(0x83, msr|0x10); /* enable write allocate */ |
| 849 | intr_restore(saveintr); |
| 850 | } |
| 851 | } |
| 852 | |
| 853 | static void |
| 854 | enable_K6_wt_alloc(void) |
no test coverage detected