Functions — github.com/ben-j-c/verilog2factorio

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Functions739 in github.com/ben-j-c/verilog2factorio

⨍ Functions 739◇ Types & classes 156

Functionadffe_program_mem_cell

()

src/tests/logical_design_tests.rs:1522

Functionadjacency_to_edges_global_edges

( partition_global_connectivity: &Vec<Vec<Vec<(i32, usize, usize)>>>, local_to_global: &Vec<Vec<usize>>, )

src/phy/design.rs:2965

Functionall

()

tests/test_designs.rs:7

Functionalu_example

()

examples/alu_example.rs:6

Methodapply

(des: &mut CheckedDesign, mapped_design: &MappedDesign)

src/checked_design/checked_design_optimizations.rs:12

Functionarith_expr

()

src/tests/logical_design_tests.rs:1855

Functionarith_stress_test

()

src/tests/logical_design_tests.rs:1879

Methodassert_is_wire_sum

(&self, id: NodeId)

src/logical_design.rs:3796

Functionbasics_example

()

examples/basics_example.rs:7

Methodbuild_from

Automatically build from a [`CheckedDesign`]

src/logical_design.rs:675

Methodbuild_from

(&mut self, _mapped_design: &MappedDesign)

src/checked_design.rs:1107

Functionbyte_select

()

src/tests/logical_design_tests.rs:1236

Methodcalculate_electrostatic_force

(&self)

src/phy/placement2.rs:225

Functioncoarsen_0

()

src/connected_design.rs:532

Functioncoarsen_1_bit

()

src/connected_design.rs:547

Functioncoarsen_complex

()

src/connected_design.rs:623

Functioncoarsen_no_shift

()

src/connected_design.rs:576

Functioncomb_pair

()

src/phy/design.rs:3190

Methodcompare_vcd_val_to_i32

(actual: i32, expected: &Option<Vec<Value>>)

src/sim.rs:1352

Methodcompute_cost

(&self, connections: &Vec<(usize, usize)>)

src/phy/placement2.rs:151

Methodcompute_networks

(logd: &LogicalDesign)

src/phy/design.rs:141

Methodconnect

Connect the red wires from `out_node` to `in_node`. e.g., if `out_node` is an arithmetic combinator and `in_node` is a red wire, then the red terminal

src/logical_design.rs:742

Methodconnect

( &mut self, from: &egui_snarl::OutPin, to: &egui_snarl::InPin, snarl: &mut egui_snarl::Snarl<Node>,

src/gui.rs:577

Functionconstant_through_nop

()

src/tests/sim_tests.rs:84

Functionconstruct_bidirectional_join

( lhs: &[S1], rhs: &[S2], )

src/util.rs:23

Functioncrack_in_two_method

( rng: &mut StdRng, _curr: &Placement, new: &mut Placement, _connections_per_node: &Vec<Vec<usize>>, side

src/phy/placement.rs:156

Functioncsr

()

src/phy/partition.rs:299

Functioncsr2

()

src/phy/partition.rs:308

Functiondecider_each1

()

src/tests/sim_tests.rs:311

Functiondecider_each2

()

src/tests/sim_tests.rs:360

Functiondecider_simple

()

src/tests/sim_tests.rs:152

Functiondecider_simple2

()

src/tests/sim_tests.rs:185

Functiondecider_simple3

()

src/tests/sim_tests.rs:219

Functiondecider_simple4

()

src/tests/sim_tests.rs:264

src/logical_design.rs:430

src/checked_design.rs:352

Methoddefault

()

src/phy/config.rs:134

src/logical_design/arithmetic_parser.rs:24

Methoddefault

()

src/logical_design/decider_parser.rs:205

Functiondelay_correctness

()

src/tests/sim_tests.rs:20

Functiondemux

()

src/tests/logical_design_tests.rs:1354

Functiondense_memory_n_mcmc

()

src/phy/design.rs:3145

Methoddeserialize

(deserializer: D)

src/mapped_design.rs:656

Functiondesign1

()

src/connected_design.rs:780

Functiondesign_balancer

()

src/tests/checked_design_tests.rs:81

Functiondesign_complex_expr

()

src/tests/checked_design_tests.rs:63

Functiondesign_simple_lut

()

src/tests/checked_design_tests.rs:135

Functiondesign_simple_lut_alterante

()

src/tests/checked_design_tests.rs:153

Functiondesign_single_dff

()

src/tests/checked_design_tests.rs:99

Functiondesign_swizzle_bits

()

src/tests/checked_design_tests.rs:117

Functiondesign_test1

()

src/mapped_design.rs:1269

Functiondesign_test1

()

src/tests/checked_design_tests.rs:9

Functiondesign_test2

()

src/tests/checked_design_tests.rs:27

Functiondesign_test3

()

src/tests/checked_design_tests.rs:45

Functiondff

()

src/tests/logical_design_tests.rs:290

Methoddisconnect

( &mut self, from: &egui_snarl::OutPin, to: &egui_snarl::InPin, snarl: &mut egui_snarl::Snarl<Node>,

src/gui.rs:630

Methoddistribute_conj

(&self, term: &DeciderConj)

src/logical_design/decider_parser.rs:98

Methoddraw_placement

( &self, connections: &Vec<(usize, usize)>, filename: &str, )

src/phy/placement2.rs:375

(&self, other: &SignalTable)

src/lua.rs:58

Methodeq

(&self, other: &Self)

src/sim.rs:1629

Methodeq

(&self, other: &Self)

src/phy/route.rs:20

Methodexecute_arith_op

(left: i32, op: ArithmeticOperator, right: i32)

src/sim.rs:524

Methodexecute_decider_op

(left: i32, op: DeciderOperator, right: i32)

src/sim/decider_model.rs:12

Methodexpecting

(&self, formatter: &mut std::fmt::Formatter)

src/mapped_design.rs:664

Methodextend

(&mut self, other: LogicalDesign, port_prefix: &str)

src/logical_design.rs:4435

Methodextend_dim0

(&mut self, extension: usize)

src/ndarr.rs:60

Methodfmt

(&self, f: &mut std::fmt::Formatter<'_>)

src/logical_design.rs:647

Methodfmt

(&self, f: &mut std::fmt::Formatter<'_>)

src/mapped_design.rs:702

Methodfmt

(&self, f: &mut std::fmt::Formatter<'_>)

src/sim.rs:1652

Methodfmt

(&self, f: &mut std::fmt::Formatter<'_>)

src/connected_design.rs:500

Methodformat_comb_hint

( sim: Option<&SimState>, ld: &LogicalDesign, id: NodeId, )

src/phy/design.rs:1431

Methodfrom

(value: crate::Error)

src/lua.rs:42

Methodfrom

(v: NodeId)

src/logical_design.rs:440

Methodfrom

(value: serde_json::Error)

src/lib.rs:65

Methodfrom

(val: (f64, f64))

src/serializable_design.rs:215

Methodfrom_args

(left: Signal, op: DeciderOperator, right: Signal)

src/logical_design/decider_parser.rs:315

Methodfrom_initialization

(assignments: Vec<(Num, Num)>, side_length: Num)

src/phy/placement.rs:741

Methodfrom_lua

(value: Value, _lua: &Lua)

src/lua.rs:152

Methodget_bfs_order

(coid: usize, connections: &Vec<Vec<usize>>)

src/phy/design.rs:1783

Functionget_connected_combs

()

src/tests/logical_design_tests.rs:467

Methodget_connectivity_as_edges

( &self, ld: &LogicalDesign, triangular: bool, )

src/phy/design.rs:1910

Methodget_connectivity_as_matrix

( &self, ld: &LogicalDesign, triangular: bool, )

src/phy/design.rs:1892

Methodget_constant

(&self)

src/connected_design.rs:483

Methodget_driver_unwrap

( &self, bit_map: &Vec<Vec<Vec<NodeId>>>, io_map: &Vec<NodeIo>, ioid: NodeId, bit_number: usize, )

src/connected_design.rs:369

Methodget_fanin_green

(&self, id: NodeId)

src/logical_design.rs:4358

Methodget_fanin_network

(&self, ldid: NodeId, colour: WireColour)

src/logical_design.rs:4225

Methodget_fanin_red

(&self, id: NodeId)

src/logical_design.rs:4353

Methodget_fanout_green

(&self, id: NodeId)

src/logical_design.rs:4348

Methodget_fanout_network

(&self, ldid: NodeId, colour: WireColour)

src/logical_design.rs:4236

Methodget_initializations

(local_connectivity: &Vec<Vec<usize>>)

src/phy/design.rs:343

Methodget_named_node

(&self, name: S)

src/logical_design.rs:4417

Methodget_yosys_display_name

(&self, name: &str)

src/mapped_design.rs:452

(&mut self, _node: &Node)

src/gui.rs:718

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