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github.com/ben-j-c/verilog2factorio
/ functions
Functions
739 in github.com/ben-j-c/verilog2factorio
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Functions
739
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Types & classes
156
Method
has_graph_menu
(&mut self, _pos: egui::Pos2, _snarl: &mut egui_snarl::Snarl<Node>)
src/gui.rs:673
Method
has_node_menu
(&mut self, _node: &Node)
src/gui.rs:739
Method
have_shared_wire
(&self, ldid_1: NodeId, ldid_2: NodeId)
src/logical_design.rs:4125
Method
have_shared_wire_detailed
( &self, id1: NodeId, id2: NodeId, colour: WireColour, id1_input: bool, id2_input: bool, )
src/logical_design.rs:4164
Method
id
(&self)
src/logical_design.rs:157
Method
import
(buf_reader: R)
src/sim/vcd.rs:17
Method
index
(&self, index: i32)
src/sim.rs:1637
Method
index
(&self, index: usize)
src/ndarr.rs:14
Method
index_mut
(&mut self, index: i32)
src/sim.rs:1646
Method
index_mut
(&mut self, index: usize)
src/ndarr.rs:20
Method
input
(colour: ld::WireColour)
src/phy/design.rs:49
Function
input_to_input
()
src/tests/logical_design_tests.rs:344
Method
inputs
(&mut self, node: &Node)
src/gui.rs:507
Method
is_all_constants
(&self)
src/mapped_design.rs:141
Method
is_all_constants
(&self)
src/connected_design.rs:479
Method
is_any
(&self)
src/logical_design.rs:178
Method
is_comb
(&self)
src/phy/design.rs:3093
Method
is_constant
(&self)
src/logical_design.rs:164
Method
is_driver
(&self)
src/connected_design.rs:94
Method
is_each
(&self)
src/logical_design.rs:171
Method
is_everything
(&self)
src/logical_design.rs:185
Method
is_port
(&self, id: NodeId)
src/logical_design.rs:4427
Function
kernighan_lin
( nodes: &Vec<usize>, connectivity: &Vec<Vec<usize>>, )
src/phy/partition.rs:6
Function
latch
()
src/tests/logical_design_tests.rs:310
Function
loopback
()
src/tests/logical_design_tests.rs:244
Function
main
()
src/main.rs:9
Function
main
()
examples/riscv.rs:5
Function
main
()
examples/basics_example.rs:30
Function
main
()
examples/yosys_example.rs:33
Function
main
()
examples/riscv_sys_verify.rs:4
Function
make_complex_40_design
()
src/lib.rs:319
Function
make_simple_design
()
src/lib.rs:308
Function
make_single_combinator
()
src/lib.rs:296
Method
max_allowable_distance
( &self, logical: &LogicalDesign, id_comb_a: PhyId, id_comb_b: PhyId, )
src/phy/design.rs:1252
Method
max_id
(&self)
src/connected_design.rs:133
Function
memory_n_mcmc
()
src/phy/design.rs:3136
Function
metis_2d_synthetic
()
src/phy/partition.rs:397
Function
metis_n_synthetic
()
src/phy/partition.rs:385
Function
metis_simple
()
src/phy/partition.rs:365
Function
multiport
()
src/mapped_design.rs:1289
Function
multiport_ram
()
src/mapped_design.rs:1328
Function
n_combs
()
src/phy/design.rs:3125
Function
named_signals
()
src/tests/logical_design_tests.rs:490
Method
needs_compaction
(&self)
src/logical_design.rs:4536
Method
new
()
src/svg.rs:82
Method
new
New blank design.
src/logical_design.rs:663
Method
new
()
src/serializable_design.rs:258
Method
new
(logd: Arc<RwLock<LogicalDesign>>)
src/sim.rs:161
Method
new
(cc: &eframe::CreationContext<'_>)
src/gui.rs:48
Method
new
(dims: [usize; 2])
src/ndarr.rs:43
Method
new
()
src/connected_design.rs:120
Method
new
()
src/checked_design.rs:358
Method
new
()
src/phy/design.rs:191
Method
new
(x: f32, y: f32, w: f32, h: f32)
src/phy/placement2.rs:19
Method
new_grid
(cell_width: i32, cell_height: i32, margin: i32)
src/svg.rs:86
Method
next
(&mut self)
src/phy/design.rs:3001
Method
nodes_n_hops_back
(&self, id: NodeId, max_hops: usize)
src/checked_design.rs:2607
Function
nop_to_lamp
()
src/tests/logical_design_tests.rs:571
Method
num_cells
(&self)
src/phy/placement2.rs:115
Method
num_terms
(&self)
src/logical_design/decider_parser.rs:209
Function
objective
(trial: tuna.trial.Trial)
hyperparameter/main.py:8
Function
ops
()
src/phy/placement.rs:2039
Method
output_combinator
(color: ld::WireColour)
src/phy/design.rs:56
Method
output_constant
(color: ld::WireColour)
src/phy/design.rs:63
Function
output_to_input
()
src/tests/logical_design_tests.rs:221
Function
output_to_output
()
src/tests/logical_design_tests.rs:329
Method
outputs
(&mut self, node: &Node)
src/gui.rs:542
Function
overflowing_cells_swap_local_method
( rng: &mut StdRng, _curr: &Placement, new: &mut Placement, _connections_per_node: &Vec<Vec<usize>>, side
src/phy/placement.rs:329
Function
parser
()
src/logical_design/arithmetic_parser.rs:136
Function
parser1
()
src/tests/logical_design_tests.rs:1316
Method
pick_colour
(ld: &LogicalDesign, id: NodeId)
src/phy/design.rs:1458
Method
pin_applies
(des: &CheckedDesign, body: ImplementableOp, input: NodeId)
src/checked_design/checked_design_optimizations.rs:62
Method
placeholder
( left: Signal, op: DeciderOperator, right: Signal, left_placeholder: Option<usize>, right_placehold
src/logical_design/decider_parser.rs:185
Function
pmux
()
src/tests/sim_tests.rs:459
Function
pmux_n
()
src/tests/sim_tests.rs:519
Method
ports
(x: A)
src/mapped_design.rs:236
Method
print_ascii_global_space
(&self)
src/phy/design.rs:2087
Function
ram
()
src/tests/logical_design_tests.rs:505
Function
ram_resetable_dense
()
src/tests/logical_design_tests.rs:1427
Function
ram_resetable_dense_full
()
src/tests/logical_design_tests.rs:1691
Function
red_green_wires
()
src/tests/logical_design_tests.rs:273
Function
remove_non_unique
(vec: Vec<T>)
src/phy/design.rs:3083
Function
render
(frame: &mut Frame)
src/sim/tui.rs:42
Method
render
(self, area: Rect, buf: &mut Buffer)
src/sim/tui.rs:78
Function
ripup_range_method
( rng: &mut StdRng, _curr: &Placement, new: &mut Placement, _connections_per_node: &Vec<Vec<usize>>, side
src/phy/placement.rs:121
Function
ripup_replace_method
( rng: &mut StdRng, _curr: &Placement, new: &mut Placement, _connections_per_node: &Vec<Vec<usize>>, side
src/phy/placement.rs:11
Function
rom_dense_large
()
src/tests/logical_design_tests.rs:431
Function
rom_dense_simple
()
src/tests/logical_design_tests.rs:399
Function
rom_simple
()
src/tests/logical_design_tests.rs:367
Method
save
(&mut self, storage: &mut dyn eframe::Storage)
src/gui.rs:89
Method
seconds
(v: i32)
src/timing_engine.rs:16
Method
seq_num
(&self)
src/sim.rs:157
Method
serialize
(&self, serializer: S)
src/serializable_design.rs:37
Method
set_description
(&mut self, description: &str)
src/serializable_design.rs:272
Method
show_body
( &mut self, node: egui_snarl::NodeId, inputs: &[egui_snarl::InPin], outputs: &[egui_snarl::OutPin],
src/gui.rs:722
Method
show_graph_menu
( &mut self, pos: egui::Pos2, ui: &mut egui::Ui, snarl: &mut egui_snarl::Snarl<Node>, )
src/gui.rs:677
Method
show_input
( &mut self, pin: &egui_snarl::InPin, _ui: &mut egui::Ui, snarl: &mut egui_snarl::Snarl<Node>, )
src/gui.rs:519
Method
show_node_menu
( &mut self, nodeid: egui_snarl::NodeId, _inputs: &[egui_snarl::InPin], _outputs: &[egui_snarl::OutPin
src/gui.rs:743
Method
show_output
( &mut self, pin: &egui_snarl::OutPin, _ui: &mut egui::Ui, snarl: &mut egui_snarl::Snarl<Node>, )
src/gui.rs:554
Function
sim_dff
()
src/tests/logical_design_tests.rs:585
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