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895 symbols 3,445 edges 43 files 51 documented · 6%

What it actually does AI analysis from the code graph — generated when you open this

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Extension points exported contracts — how you extend this code

Optimization (Interface)

(no doc) [8 implementers]

src/checked_design/checked_design_optimizations.rs

BitSliceOps (Interface)

(no doc) [2 implementers]

src/mapped_design.rs

Topology (Interface)

(no doc) [1 implementers]

src/phy/route.rs

FromBinStr (Interface)

(no doc) [1 implementers]

src/mapped_design.rs

TopologyIndex (Interface)

(no doc) [1 implementers]

src/phy/route.rs

IntoBoolVec (Interface)

(no doc) [1 implementers]

Core symbols most depended-on inside this repo

add_wire_red

called by 164

src/logical_design.rs

src/logical_design.rs

src/logical_design.rs

set_description_node

called by 86

src/logical_design.rs

add_constant

called by 73

src/logical_design.rs

Shape

Method 528

Function 211

Class 126

Enum 23

Interface 7

Languages

Rust100%

Python1%

Modules by API surface

src/logical_design.rs165 symbols

src/phy/design.rs98 symbols

src/checked_design.rs64 symbols

src/sim.rs60 symbols

src/mapped_design.rs58 symbols

src/tests/logical_design_tests.rs41 symbols

src/gui.rs38 symbols

src/phy/placement.rs35 symbols

src/serializable_design.rs34 symbols

src/phy/placement2.rs28 symbols

src/connected_design.rs28 symbols

src/lua.rs26 symbols

For agents

$ claude mcp add verilog2factorio \
  -- python -m otcore.mcp_server <graph>

⬇ download graph artifact