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Functions739 in github.com/ben-j-c/verilog2factorio

⨍ Functions 739◇ Types & classes 156

↓ 1 callersMethodget_out_port_nodes

src/logical_design.rs:4391

↓ 1 callersMethodget_partition_id_mapping

Return two maps. First one local_to_global[partition][local_id] -> global_id. Second one global_to_local[partition][global_id] -> local_id. local_id :

src/phy/design.rs:1807

↓ 1 callersMethodget_port

(&'a self, port_name: &str)

src/mapped_design.rs:591

↓ 1 callersMethodget_seen_each_on_conditions

( &self, node: NodeId, each_seen_colours: (bool, bool), )

src/sim/decider_model.rs:187

↓ 1 callersMethodget_sigular_output_input_pair

see [`count_connected_terminals`] */

src/checked_design.rs:2548

↓ 1 callersMethodget_source_delay

(&self, node: NodeId)

src/timing_engine.rs:48

↓ 1 callersMethodget_top_source

src/mapped_design.rs:613

↓ 1 callersMethodget_wire_network_on_cell

( &self, id: NodeId, colour: WireColour, direction: Direction, )

src/logical_design.rs:4319

↓ 1 callersMethodget_wire_networks

src/phy/design.rs:1665

↓ 1 callersMethodglobal_freeze

( &mut self, logical: &LogicalDesign, margin: usize, partition_dims: (usize, usize), local_to_global

src/phy/design.rs:2028

↓ 1 callersMethodglobal_freeze_and_route2

( &mut self, logical: &LogicalDesign, local_to_global: &Vec<Vec<usize>>, _global_to_local: &Vec<HashM<

src/phy/design.rs:2410

↓ 1 callersMethodhandle_key_event

(&mut self, key_event: KeyEvent)

src/sim/tui.rs:68

↓ 1 callersMethodhas_errors

↓ 1 callersMethodhave_shared_wire_discriminate_side

( &self, ldid_1: NodeId, ldid_2: NodeId, )

src/logical_design.rs:4130

↓ 1 callersMethodheight

src/phy/design.rs:221

↓ 1 callersMethodheuristic

(&self, a: &SpaceIndex, b: &SpaceIndex)

src/phy/design.rs:3025

↓ 1 callersMethodidentify_clocks

(&mut self, mapped_design: &MappedDesign)

src/checked_design.rs:2584

↓ 1 callersMethodincrement_placeholder

(&self, count: usize)

src/logical_design/decider_parser.rs:345

↓ 1 callersMethodinitialize_nodes

(&mut self, mapped_design: &MappedDesign)

src/checked_design.rs:474

↓ 1 callersMethodinput

(&self, colour: WireColour)

↓ 1 callersMethodinspect

src/sim.rs:1379

↓ 1 callersMethodis_constant

src/connected_design.rs:98

↓ 1 callersMethodis_dff

src/checked_design.rs:179

↓ 1 callersMethodis_non_zero

src/mapped_design.rs:108

↓ 1 callersMethodis_output

src/checked_design.rs:240

↓ 1 callersFunctionload_bin_file

src/util.rs:101

↓ 1 callersFunctionload_hex_file

↓ 1 callersFunctionload_snapshot

src/sim/snapshot.rs:70

↓ 1 callersFunctionload_trace

src/sim/snapshot.rs:86

↓ 1 callersFunctionmain

hyperparameter/main.py:58

↓ 1 callersFunctionmain

examples/alu_example.rs:15

↓ 1 callersMethodmake_assertions

(&self, _logical: &LogicalDesign)

src/phy/design.rs:2894

↓ 1 callersMethodmake_preliminary_connections

src/checked_design.rs:615

↓ 1 callersFunctionmapped_flow

↓ 1 callersMethodmax_bit

src/mapped_design.rs:507

↓ 1 callersFunctionmethod_load_mapped_rtl

( mapped_json: &P, )

↓ 1 callersFunctionmethod_sim_yosys

(filename_in: &str, filename_out: &str)

↓ 1 callersMethodneighbors

Horribly inefficient. but w/e, we will see how slow.

src/phy/design.rs:3010

↓ 1 callersMethodoptimize_graph

(&mut self, mapped_design: &MappedDesign)

src/checked_design.rs:2561

↓ 1 callersMethodpartition

(&mut self, ld: &LogicalDesign, target_size: i32)

src/phy/design.rs:1928

↓ 1 callersMethodpartition_io_network

(&mut self, mut local_io: Vec<NodeId>)

src/checked_design.rs:1211

↓ 1 callersMethodplace_global

( &mut self, partitions_global_connectivity: &Vec<Vec<Vec<(i32, usize, usize)>>>, )

src/phy/design.rs:1986

↓ 1 callersMethodplace_local

( &mut self, logical: &LogicalDesign, partition_local_connectivity: &Vec<Vec<Vec<usize>>>, partition_g

src/phy/design.rs:431

↓ 1 callersMethodprobe_out_state_red

(&self, id: NodeId)

↓ 1 callersFunctionreduce_prescedence

(operands: &mut [ArithExpr], ops: &[ArithmeticOperator])

src/logical_design/arithmetic_parser.rs:280

↓ 1 callersMethodreinit_logd

(&mut self, clone: Arc<RwLock<LogicalDesign>>)

src/sim.rs:1497

↓ 1 callersMethodremove_decider_output

(&mut self, id: NodeId, idx: usize)

src/logical_design.rs:3473

↓ 1 callersMethodreport_timing_save_worst_path

(&self, logd: &LogicalDesign, mapped_design: &MappedDesign)

src/checked_design.rs:2632

↓ 1 callersMethodreset_network_connectivity

(&mut self, start: usize)

↓ 1 callersMethodreset_place_route

src/phy/design.rs:1271

↓ 1 callersMethodresolve_coarse_exprs

src/checked_design.rs:633

↓ 1 callersMethodresolve_control_behaviour

(&self, logical: &LogicalDesign)

src/serializable_design.rs:361

↓ 1 callersMethodresolve_description

(&self, logical: &LogicalDesign)

src/serializable_design.rs:357

↓ 1 callersMethodresolve_name

(&self, logical: &LogicalDesign)

src/serializable_design.rs:346

↓ 1 callersFunctionrgba_to_string

(c: (u8, u8, u8, f32))

↓ 1 callersMethodroute_nets

(&mut self, logical: &LogicalDesign)

src/phy/design.rs:2120

↓ 1 callersMethodroute_single_net

( &mut self, logical: &LogicalDesign, id_1: NodeId, dir_1: Direction, id_2: NodeId, dir_2: Directi

src/phy/design.rs:2526

↓ 1 callersFunctionrun_tui

(logd: Arc<RwLock<LogicalDesign>>, sim: Arc<RwLock<SimState>>)

src/sim/tui.rs:22

↓ 1 callersFunctionsave_dot

( design: &CheckedDesign, mapped: &MappedDesign, filter: Option<&HashS<usize>>, filepath: &str, )

src/checked_design.rs:2920

↓ 1 callersFunctionsave_memh_file

(path: P, data: Vec<i32>)

src/util.rs:116

↓ 1 callersMethodset_constants_output

(&mut self, nodeid: NodeId, sigs: Vec<Signal>, vals: Vec<i32>)

src/logical_design.rs:3828

↓ 1 callersMethodset_signal

(&self, signals: &mut Vec<Signal>, nodeid: NodeId, signal: Signal)

src/checked_design.rs:1319

↓ 1 callersFunctionshow_node_config

( logd: &mut LogicalDesign, node: egui_snarl::NodeId, _inputs: &[egui_snarl::InPin], _outputs: &[egui_snar

↓ 1 callersFunctionshow_node_sim_state

( logd: &LogicalDesign, sim: &mut Option<(SimState, SimSettings)>, node: egui_snarl::NodeId, _inputs: &[eg

↓ 1 callersMethodsignals_correctness_check

(&self, signal_choices: &[Signal])

src/checked_design.rs:1047

↓ 1 callersFunctionsimple_kmeans_balance_partitions

(data: &DMatrix<f64>, k: usize)

src/phy/partition.rs:111

↓ 1 callersMethodsolve_analytical_dense

( &self, logical: &LogicalDesign, connections_per_node: &Vec<Vec<usize>>, global_connectivity: &Vec<Ve

src/phy/design.rs:544

↓ 1 callersFunctionsource_link

(ui: &mut egui::Ui)

↓ 1 callersFunctionspectral_k_way

(connectivity: &Vec<Vec<usize>>, k: i32)

src/phy/partition.rs:203

↓ 1 callersMethodsplit_connections_to_local_and_global

( &self, global_connections: &Vec<Vec<usize>>, )

src/phy/design.rs:1838

↓ 1 callersMethodstep_cells

(&mut self, force: Vec<(f32, f32)>, factor: f32)

src/phy/placement2.rs:451

↓ 1 callersMethodsub_placeholder

(&self, repl: Signal, ident: usize)

src/logical_design/decider_parser.rs:293

↓ 1 callersMethodterminal_direction

(&self, terminal_name: &str)

src/connected_design.rs:357

↓ 1 callersMethodterminal_direction_by_id

(&self, terminal_number: usize)

src/connected_design.rs:361

↓ 1 callersMethodterminal_number

(&self, terminal_name: &str)

src/connected_design.rs:365

↓ 1 callersMethodtitle

(&mut self, node: &Node)

↓ 1 callersMethodto_pair

src/phy/design.rs:2989

↓ 1 callersMethodtruncate

(&mut self, offset: usize, offset_ports: usize)

src/logical_design.rs:4463

↓ 1 callersMethodunwrap_arithmetic

src/logical_design.rs:294

↓ 1 callersMethodunwrap_arithmetic_mut

src/logical_design.rs:358

↓ 1 callersMethodunwrap_constant_mut

src/logical_design.rs:387

↓ 1 callersMethodunwrap_constant_value

src/connected_design.rs:102

↓ 1 callersMethodunwrap_decider_mut

src/logical_design.rs:323

↓ 1 callersMethodunwrap_display_panel_mut

src/logical_design.rs:403

↓ 1 callersMethodunwrap_lamp_mut

src/logical_design.rs:395

↓ 1 callersMethodunwrap_vec_mut

src/checked_design.rs:326

↓ 1 callersMethodupdate_folded_data

src/checked_design.rs:2900

↓ 1 callersFunctionupdate_folded_data_isotropic_ports

(data: &mut FoldedData, signals: Vec<Signal>)

src/checked_design/checked_design_optimizations.rs:477

↓ 1 callersFunctionupdate_folded_data_mux

(node: &mut Node, signals: Vec<Signal>)

src/checked_design/checked_design_optimizations.rs:493

↓ 1 callersMethodupdate_folded_data_node

(&mut self, id: NodeId)

src/checked_design.rs:2868

↓ 1 callersFunctionupdate_folded_data_pmux

( node: &mut Node, signals: Vec<Signal>, full_case: bool, width: usize, )

src/checked_design/checked_design_optimizations.rs:503

↓ 1 callersMethodvalidate_against

(&self, logd: &LogicalDesign)

src/phy/design.rs:1611

( topology: &'a T, a: &X, b: &X, relaxion_param: Option<f32>, )

src/phy/route.rs:72

Methodadd_fields

(fields: &mut F)

Methodadd_fields

(fields: &mut F)

src/lua/physical_ensemble.rs:353

Methodadd_methods

(methods: &mut M)

Methodadd_methods

(methods: &mut M)

src/lua/physical_ensemble.rs:103

Methodadd_mux_internal

(&mut self, data: Signal, s: Signal)

src/logical_design.rs:1727

Methodadd_pmux_slow

( &mut self, a: Option<Signal>, b: &[Signal], s: &[Signal], y: Signal, s_folded_expr: Option<&[Opt

src/logical_design.rs:1437

Methodadd_wire_green_on_input

(&mut self, comb: NodeId)

src/logical_design.rs:3656

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