Functions — github.com/ben-j-c/verilog2factorio

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Functions739 in github.com/ben-j-c/verilog2factorio

⨍ Functions 739◇ Types & classes 156

↓ 2 callersFunctionrgb_to_string

(c: (u8, u8, u8))

src/svg.rs:736

↓ 2 callersMethodroute_partial_net

( &mut self, terminals: &Vec<(Direction, NodeId)>, connected_map: &Vec<Option<usize>>, idx_1: usize,

src/phy/design.rs:2456

↓ 2 callersMethodsave_svg_full

( &self, sim: Option<&SimState>, ld: &LogicalDesign, filename: P, )

src/phy/design.rs:1420

↓ 2 callersMethodset_description

(&mut self, description: String)

src/logical_design.rs:3824

↓ 2 callersMethodset_group_io

(&mut self, group_io: bool)

src/phy/design.rs:229

↓ 2 callersMethodset_node_coarse_expr

(&mut self, id: NodeId, expr: CoarseExpr)

src/checked_design.rs:412

↓ 2 callersFunctionsignal_parser_no_constant

( )

src/logical_design/arithmetic_parser.rs:68

↓ 2 callersMethodunwrap_mask_shift

(&self)

src/connected_design.rs:78

↓ 2 callersFunctionverify_is_combinator

(_this: &SimStateAPI, data: &Value)

src/lua.rs:971

↓ 2 callersMethodxy

(&self)

src/phy/placement2.rs:58

↓ 2 callersMethodxy_plus_wh

(&self)

src/phy/placement2.rs:62

↓ 1 callersMethodadd_animation_step_line

(&mut self, id: ShapeId, pos1: (i32, i32), pos2: (i32, i32))

src/svg.rs:396

↓ 1 callersMethodadd_animation_step_rect

(&mut self, id: ShapeId, pos: (i32, i32))

src/svg.rs:387

↓ 1 callersMethodadd_arithmetic

(&mut self)

src/gui.rs:409

↓ 1 callersMethodadd_binary_op

( &mut self, op: ImplementableOp, sig_left: Signal, sig_right: Signal, sig_out: Signal, )

src/logical_design.rs:788

↓ 1 callersMethodadd_constant

(&mut self)

src/gui.rs:422

↓ 1 callersMethodadd_decider

(&mut self)

src/gui.rs:397

↓ 1 callersMethodadd_display_panel

(&mut self)

src/gui.rs:439

↓ 1 callersMethodadd_edge_detector

(&mut self, clk_in: Signal)

src/logical_design.rs:4090

↓ 1 callersMethodadd_lamp

(&mut self)

src/gui.rs:430

↓ 1 callersMethodadd_line_stroke_dasharray

( &mut self, x1: i32, y1: i32, x2: i32, y2: i32, colour: Option<String>, width: Option<i32>, s

src/svg.rs:206

↓ 1 callersMethodadd_lut

A pattern for a lookup table. ehhhhh too lazy to spec it now. Raise an issue if you want me to.

src/logical_design.rs:3858

↓ 1 callersMethodadd_mux

( &mut self, a: Signal, b: Signal, s: Signal, y: Signal, s_folded_expr: Option<&DeciderSop>, )

src/logical_design.rs:1835

↓ 1 callersMethodadd_nop_with_wire

Add a combinator fitting the pattern that I call "no-operation". Converts the input signal to an output signal using an arithmetic combinator. Return

src/logical_design.rs:882

↓ 1 callersMethodadd_reduce_and

(&mut self, a: &[Signal], y: Signal)

src/logical_design.rs:3995

↓ 1 callersMethodadd_reduce_or

(&mut self, a: &[Signal], y: Signal)

src/logical_design.rs:4021

↓ 1 callersFunctionadd_signal_input_box_name_only_label

( ui: &mut egui::Ui, signal: &mut Signal, text: &mut String, name: &str, )

src/gui.rs:1144

↓ 1 callersMethodadd_sop_not

( &mut self, sig_in: Vec<Signal>, sig_out: Signal, sig_out_bar: Signal, table: Vec<bool>, depth: u

src/logical_design.rs:3979

↓ 1 callersMethodadd_unary_op

( &mut self, op: ImplementableOp, sig_in: Signal, sig_out: Signal, )

src/logical_design.rs:818

↓ 1 callersMethodadd_v2f_ram

( &mut self, read_addr: &[Signal], read_data: &[Signal], clk: Signal, write_ports: Vec<MemoryWritePo

src/logical_design.rs:2991

↓ 1 callersMethodadd_v2f_rom

( &mut self, addr: Signal, data: Signal, rom_values: Vec<i32>, )

src/logical_design.rs:2944

↓ 1 callersMethodadd_wire

( &mut self, a: ShapeId, b: ShapeId, attachment_a: u32, attachment_b: u32, )

src/svg.rs:231

↓ 1 callersMethodadd_wire_floating_green

(&mut self)

src/logical_design.rs:3771

↓ 1 callersMethodadd_wire_green_safe

( &mut self, fanin: Vec<NodeId>, fanout: Vec<NodeId>, )

src/logical_design.rs:3687

↓ 1 callersMethodadd_wire_green_tie_inputs

It has the same behaviour as a wire in game. Attach the inputs of two combinators together. Returns the id for the wire you created.

src/logical_design.rs:3729

↓ 1 callersMethodadd_wire_green_tie_outputs

It has the same behaviour as a wire in game. Attach the outputs of two combinators together. Returns the id for the wire you created.

src/logical_design.rs:3722

↓ 1 callersMethodadd_wire_red_safe

( &mut self, fanin: Vec<NodeId>, fanout: Vec<NodeId>, )

src/logical_design.rs:3606

↓ 1 callersFunctionadjacency_to_edges_weighted

( conn_list: &Vec<Vec<(usize, usize)>>, triangular: bool, )

src/phy/design.rs:2933

↓ 1 callersFunctionapp

( terminal: &mut DefaultTerminal, logd: Arc<RwLock<LogicalDesign>>, phy: Arc<RwLock<SimState>>, )

src/sim/tui.rs:29

↓ 1 callersMethodapply_multipart_op

( &self, nodeid: NodeId, logical_design: &mut LogicalDesign, _mapped_design: &MappedDesign, op: Impl

src/checked_design.rs:1849

↓ 1 callersMethodapply_onto

(&self, logical_design: &mut LogicalDesign, mapped_design: &MappedDesign)

src/checked_design.rs:1564

↓ 1 callersMethodapply_trace

(&mut self, trace: &GameTrace, reset: bool)

src/sim.rs:1278

↓ 1 callersMethodapply_vcd

( &mut self, vcd: &VCD, inputs: HashM<String, NodeId>, outputs: HashM<String, (Signal, NodeId)>, pro

src/sim.rs:1141

↓ 1 callersMethodbool_unwrap

(&self)

src/mapped_design.rs:100

↓ 1 callersMethodbuild_copper_network

(&self)

src/phy/design.rs:2666

↓ 1 callersMethodcalculate_accessibility_force

( &self, connctions: &Vec<Vec<(i32, usize, usize)>>, )

src/phy/placement2.rs:326

↓ 1 callersMethodcalculate_and_validate_signal_choices

(&self, mapped_design: &MappedDesign)

src/checked_design.rs:883

↓ 1 callersMethodcalculate_buckling_force

(&self)

src/phy/placement2.rs:293

↓ 1 callersMethodcalculate_legalization_force

(&self)

src/phy/placement2.rs:272

↓ 1 callersFunctioncalculate_minimum_partition_dim

( local_assignments: &Vec<Vec<(usize, usize)>>, )

src/phy/design.rs:2919

↓ 1 callersMethodcalculate_overlap_force

(&self)

src/phy/placement2.rs:197

↓ 1 callersMethodcalculate_radial_force

(&self)

src/phy/placement2.rs:350

↓ 1 callersMethodcalculate_spring_force

(&self, connctions: &Vec<Vec<usize>>)

src/phy/placement2.rs:248

↓ 1 callersMethodcapture_trace

(&mut self)

src/sim.rs:446

↓ 1 callersMethodclear_error_is_assert

(&self)

src/sim.rs:181

↓ 1 callersMethodclear_errors

(&self)

src/sim.rs:194

↓ 1 callersMethodclose_enough_to_connect

(&self, logical: &LogicalDesign, id_i: NodeId, id_j: NodeId)

src/phy/design.rs:1339

↓ 1 callersMethodclose_enough_to_connect_phy

( &self, logical: &LogicalDesign, id_i: PhyId, id_j: PhyId, )

src/phy/design.rs:1351

↓ 1 callersMethodcompute_arithmetic_comb

( &self, node: &Node, new_state_red: &mut OutputState, new_state_green: &mut OutputState, )

src/sim.rs:631

↓ 1 callersMethodcompute_combs

( &self, new_state_red: &mut Vec<OutputState>, new_state_green: &mut Vec<OutputState>, )

src/sim.rs:775

↓ 1 callersMethodcompute_decider_comb

( &self, node: &Node, new_state_red: &mut OutputState, new_state_green: &mut OutputState, )

src/sim/decider_model.rs:338

↓ 1 callersFunctioncompute_gain

( a: usize, b: usize, a_set: &Vec<usize>, b_set: &Vec<usize>, connectivity: &Vec<Vec<usize>>, )

src/phy/partition.rs:47

↓ 1 callersFunctionconvert_lut_ports

(pre_mapped: MappedCell)

src/mapped_design.rs:1019

↓ 1 callersFunctionconvert_mem_v2

(cell: MappedCell)

src/mapped_design.rs:875

↓ 1 callersFunctionconvert_pmux_ports

(pre_mapped: MappedCell)

src/mapped_design.rs:1073

↓ 1 callersFunctionconvert_reduce_x_ports

(pre_mapped: MappedCell)

src/mapped_design.rs:1139

↓ 1 callersFunctionconvert_sop_ports

(pre_mapped: MappedCell)

src/mapped_design.rs:1046

↓ 1 callersFunctionconvert_v2f_programmable_ram

(cell: MappedCell)

src/mapped_design.rs:1171

↓ 1 callersFunctionconvert_v2f_ram

(cell: MappedCell)

src/mapped_design.rs:851

↓ 1 callersFunctionconvert_v2f_rom

(cell: MappedCell)

src/mapped_design.rs:833

↓ 1 callersMethodcopy

(&mut self, other: &Self)

src/sim.rs:1665

↓ 1 callersMethodcount_connected_terminals

Return the number of CellOutput nodes attached to the CellInput nodes on this CellBody

src/checked_design.rs:2538

↓ 1 callersMethoddelete_and_compact

(&mut self)

src/logical_design.rs:4540

↓ 1 callersMethoddir

(&self, other: (f32, f32))

src/phy/placement2.rs:73

↓ 1 callersMethoddraw

(&self, frame: &mut Frame)

src/sim/tui.rs:53

↓ 1 callersFunctiondump_phy_cfg

()

src/lib.rs:279

↓ 1 callersMethodelaborate_signal_choices

( &self, signal_choices: &mut Vec<Signal>, mapped_design: &MappedDesign, )

src/checked_design.rs:979

↓ 1 callersMethodenforce_network_requirements

(&mut self, mapped_design: &MappedDesign)

src/checked_design.rs:833

↓ 1 callersMethodexecute_decider_output_anything_model

( &self, node: &Node, output_signals: &mut OutputState, network: (bool, bool), constant: Option<i32>

src/sim/decider_model.rs:240

↓ 1 callersMethodexecute_decider_output_each_model

( &self, node: &Node, output_signals: &mut OutputState, network: (bool, bool), constant: Option<i32>

src/sim/decider_model.rs:222

↓ 1 callersMethodexecute_decider_output_everything_model

( &self, node: &Node, output_state: &mut OutputState, network: (bool, bool), constant: Option<i32>,

src/sim/decider_model.rs:23

↓ 1 callersMethodfanin_empty

Does this node not have any nodes that feed into it?

src/logical_design.rs:514

↓ 1 callersMethodfanin_first

(&self, colour: WireColour)

src/logical_design.rs:482

↓ 1 callersMethodfanout_first

Iterate the fanout of a specific colour.

src/logical_design.rs:490

↓ 1 callersMethodfill_coverage

(&mut self)

src/phy/design.rs:2560

↓ 1 callersMethodfind_wire_between_disconnect

( &mut self, first: NodeId, second: NodeId, colour: WireColour, )

src/logical_design.rs:4487

↓ 1 callersMethodfor_all_phy

(&self, mut func: F)

src/phy/design.rs:296

↓ 1 callersMethodfor_all_wires

(&self, mut func: F)

src/phy/design.rs:305

↓ 1 callersMethodget_attached

(&self, idx: usize)

src/sim.rs:1132

↓ 1 callersMethodget_clocks

(&self)

src/mapped_design.rs:422

↓ 1 callersFunctionget_complex_40_logical_design

()

src/tests/logical_design_tests.rs:37

↓ 1 callersMethodget_constant_enabled

(&mut self, nodeid: NodeId)

src/logical_design.rs:3849

↓ 1 callersMethodget_errors

(&self)

src/sim.rs:186

↓ 1 callersMethodget_groupings

(&self)

src/checked_design.rs:1461

↓ 1 callersMethodget_in_port_nodes

(&self)

src/logical_design.rs:4409

↓ 1 callersMethodget_inputs_through_body

(&self, id: NodeId)

src/checked_design.rs:1150

↓ 1 callersFunctionget_large_dense_memory_test_design

(n: usize)

src/tests/logical_design_tests.rs:158

↓ 1 callersFunctionget_large_memory_test_design

(n: usize)

src/tests/logical_design_tests.rs:128

↓ 1 callersMethodget_other_input_nodes

(&self, nodeid: NodeId)

src/checked_design.rs:1352

↓ 1 callersMethodget_other_output_nodes

(&self, nodeid: NodeId)

src/checked_design.rs:1366

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