Functions — github.com/ben-j-c/verilog2factorio

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Functions739 in github.com/ben-j-c/verilog2factorio

⨍ Functions 739◇ Types & classes 156

↓ 3 callersMethodmapped_terminal_name

(&self)

src/checked_design.rs:252

↓ 3 callersFunctionmut_idx

(data: &mut [T], idx1: usize, idx2: usize)

src/util.rs:127

↓ 3 callersMethodoverlap

https://www.desmos.com/calculator/wywzi2mula

src/phy/placement2.rs:24

↓ 3 callersMethodplace_comb_physical

( &mut self, position: (f64, f64), id_to_place: PhyId, logical: &LogicalDesign, partition_opt: Optio

src/phy/design.rs:1284

↓ 3 callersMethodplace_combs_physical_dense

( &mut self, comb_positions: &Vec<(usize, usize)>, logical: &LogicalDesign, partition: i32, local_to

src/phy/design.rs:515

↓ 3 callersMethodprobe_input_state

(&self, id: NodeId)

src/sim.rs:413

↓ 3 callersMethodreplace_placeholders

(&self, repl: &[Signal])

src/logical_design/decider_parser.rs:160

↓ 3 callersFunctionreport_partition_quality

( part: &Vec<i32>, n_cuts: i32, connectivity: &Vec<Vec<usize>>, n_parts: i32, )

src/phy/partition.rs:259

↓ 3 callersMethodsave_dot

( &self, mapped_design: &MappedDesign, filter: Option<&HashS<NodeId>>, filename: S, )

src/checked_design.rs:2575

↓ 3 callersMethodsimple_string

(&self)

src/checked_design.rs:72

↓ 3 callersFunctionspectral

(connectivity: &Vec<Vec<usize>>)

src/phy/partition.rs:76

↓ 3 callersMethodterminal_id_to_direction_colour

( &self, id: PhyId, terminal: TerminalId, logd: &LogicalDesign, )

src/phy/design.rs:1737

↓ 3 callersFunctionterminal_to_colour

(terminal: usize)

src/gui.rs:1219

↓ 3 callersMethodtry_prune

(&mut self, id: NodeId)

src/checked_design.rs:2465

↓ 3 callersMethodupdate_logical_design

(&mut self)

src/sim.rs:208

↓ 2 callersFunctiona_star_initial_set

( topology: &'a T, a: &[X], b: &[X], relaxation: Option<f32>, )

src/phy/route.rs:81

↓ 2 callersMethodadd_adffe_program_mem_cell

( &mut self, clk: Signal, en: Signal, arst: Signal, reset_value: &[i32], density: usize, )

src/logical_design.rs:1215

↓ 2 callersMethodadd_byte_select_write

( &mut self, select_packed: Signal, )

src/logical_design.rs:1887

↓ 2 callersMethodadd_cell

( &mut self, pos: Option<(f32, f32)>, (w, h): (f32, f32), fixed: bool, max_distance: f32, )

src/phy/placement2.rs:119

↓ 2 callersMethodadd_demux_memory_with_byte_select

( &mut self, addr: Signal, byte_select: Signal, density: usize, )

src/logical_design.rs:1772

↓ 2 callersMethodadd_dff_isolated

( &mut self, input: Signal, clk: Signal, output: Signal, )

src/logical_design.rs:1083

↓ 2 callersMethodadd_fill_cell

( &mut self, grid: GridSpec, x: i32, y: i32, colour: (u8, u8, u8), label: Option<String>, hover:

src/svg.rs:94

↓ 2 callersMethodadd_latch_arst

( &mut self, data: Signal, clk: Signal, arst: Signal, negative_clk_polarity: bool, negative_arst_p

src/logical_design.rs:960

↓ 2 callersMethodadd_latch_arst_mem_cell

( &mut self, clk: Signal, arst: Signal, )

src/logical_design.rs:1020

↓ 2 callersMethodadd_line_cell

( &mut self, grid: GridSpec, x1: i32, y1: i32, x2: i32, y2: i32, colour: Option<String>, width

src/svg.rs:116

↓ 2 callersMethodadd_mux_memory

(&mut self, s: Signal, n: i32)

src/logical_design.rs:1749

↓ 2 callersMethodadd_pole

(&mut self, loc: SpaceIndex, logic: NodeId)

src/phy/design.rs:2232

↓ 2 callersMethodadd_ram

( &mut self, read_ports: Vec<MemoryReadPort>, write_ports: Vec<MemoryWritePort>, size: u32, )

src/logical_design.rs:2384

↓ 2 callersMethodadd_rect_ext

( &mut self, x: i32, y: i32, w: i32, h: i32, colour: (u8, u8, u8, f32), label: Option<String>,

src/svg.rs:157

↓ 2 callersFunctionadd_signal_input_box

( ui: &mut egui::Ui, signal: &mut Signal, nets: &mut (bool, bool), text: &mut String, )

src/gui.rs:1112

↓ 2 callersFunctionadd_signal_input_box_name_only_no_constants

( ui: &mut egui::Ui, signal: &mut Signal, text: &mut String, )

src/gui.rs:1194

↓ 2 callersMethodadd_sop

( &mut self, sig_in: Vec<Signal>, sig_out: Signal, table: Vec<bool>, depth: usize, folded_expr: &F

src/logical_design.rs:3925

↓ 2 callersMethodadd_srl

(&mut self, ab: &[Signal], y: Signal)

src/logical_design.rs:4047

↓ 2 callersMethodadd_swizzle

A pattern for bit manipulations. ehhhhh too lazy to spec it now. Raise an issue if you want me to.

src/logical_design.rs:3253

↓ 2 callersMethodadd_wire

(&mut self, colour: WireColour)

src/gui.rs:449

↓ 2 callersFunctionadjacency_to_edges

( conn_list: &Vec<Vec<usize>>, triangular: bool, )

src/phy/design.rs:2949

↓ 2 callersMethodapply_legalization

(&mut self)

src/phy/placement2.rs:497

↓ 2 callersMethodarea

(self)

src/phy/placement2.rs:39

↓ 2 callersMethodbuild_from

(&mut self, physical: &PhysicalDesign, logical: &LogicalDesign)

src/serializable_design.rs:276

↓ 2 callersMethodbuild_from

(&mut self, mapped_design: &MappedDesign)

src/connected_design.rs:137

↓ 2 callersFunctioncirc_attachment

(cx: i32, cy: i32, r: i32, attachment_index: u32)

src/svg.rs:721

↓ 2 callersMethodcommit_route2

( &mut self, mut path: Vec<SpaceIndex>, terminals: &Vec<(Direction, NodeId)>, connected_map: &mut Vec<

src/phy/design.rs:2248

↓ 2 callersMethodcompute_nets

( &self, new_state_red: &mut Vec<OutputState>, new_state_green: &mut Vec<OutputState>, network_states:

src/sim.rs:808

↓ 2 callersMethodconnect_wire2

( &mut self, direction_a: Direction, id_comb_a: NodeId, direction_b: Direction, id_comb_b: NodeId,

src/phy/design.rs:1368

↓ 2 callersMethoddisconnect_and_try_prune

Looks at the cell and disconnects it from the surrounding world, then prune itself.

src/checked_design.rs:2503

↓ 2 callersMethoddistance

(&self, a: &SpaceIndex, b: &SpaceIndex)

src/phy/design.rs:3018

↓ 2 callersMethoddo_compute_step

( &self, node: &Node, new_state_red: &mut OutputState, new_state_green: &mut OutputState, )

src/sim.rs:740

↓ 2 callersFunctiondraw_trace_tick

( svg: &mut SVG, last: Option<i32>, now: i32, x: i32, y: i32, width: i32, height: i32, corner_size: i3

src/sim.rs:1560

↓ 2 callersFunctioneuclidean_distance_squared_f64_pair

(x: (f64, f64), y: (f64, f64))

src/phy/design.rs:3079

↓ 2 callersMethodevaluate_decider_condition

( &self, node: &Node, expr: &(Signal, DeciderOperator, Signal), left_network: &(bool, bool), right_n

src/sim/decider_model.rs:282

↓ 2 callersMethodget_arcs

(&self, node: NodeId)

src/timing_engine.rs:56

↓ 2 callersMethodget_arithmetic_op

(&self)

src/checked_design.rs:161

↓ 2 callersMethodget_body_type

(&self)

src/checked_design.rs:116

↓ 2 callersMethodget_cell_type

(&self)

src/checked_design.rs:260

↓ 2 callersMethodget_connectivity_as_vec

(&self, ld: &LogicalDesign)

src/phy/design.rs:1818

↓ 2 callersMethodget_constant

(&self)

src/mapped_design.rs:145

↓ 2 callersMethodget_driver

( &self, bit_map: &Vec<Vec<Vec<NodeId>>>, io_map: &Vec<NodeIo>, ioid: NodeId, bit_number: usize, )

src/connected_design.rs:386

↓ 2 callersMethodget_fanout_red

(&self, id: NodeId)

src/logical_design.rs:4343

↓ 2 callersMethodget_in_port_node

(&self, name: S)

src/logical_design.rs:4399

↓ 2 callersFunctionget_large_logical_design_2d

(n: usize)

src/tests/logical_design_tests.rs:103

↓ 2 callersMethodget_local_cell_io_network

(&self, nodeid: NodeId)

src/logical_design.rs:4254

↓ 2 callersMethodget_local_cell_io_network

(&self, nodeid: NodeId)

src/checked_design.rs:1380

↓ 2 callersMethodget_net_attribute

( &self, net_name: S1, attribute: S2, )

src/mapped_design.rs:635

↓ 2 callersMethodget_op

(&self)

src/checked_design.rs:294

↓ 2 callersMethodget_out_port_node

(&self, name: S)

src/logical_design.rs:4381

↓ 2 callersMethodget_output_signals

(&self, id: NodeId)

src/logical_design.rs:3531

↓ 2 callersMethodget_port_signal

(&self, id: NodeId)

src/logical_design.rs:4431

↓ 2 callersMethodget_sink_delay

(&self, node: NodeId)

src/timing_engine.rs:52

↓ 2 callersMethodget_terminal_for_phy

( &self, id: PhyId, dir: Direction, colour: WireColour, logical: &LogicalDesign, )

src/phy/design.rs:2383

↓ 2 callersMethodget_terminal_names

Defines the canonical ordering of ports in fanin/fanout.

src/mapped_design.rs:233

↓ 2 callersMethodget_topo_order

(&self, mapped_design: &MappedDesign)

src/checked_design.rs:1498

↓ 2 callersMethodget_wire_colour

(&self, nodeid: NodeId)

src/logical_design.rs:4247

↓ 2 callersMethodhas_var

(&self, var: S)

src/sim/vcd.rs:51

↓ 2 callersMethodid_unwrap

(&self)

src/mapped_design.rs:84

↓ 2 callersMethodincrement_placeholders

(&self, count: usize)

src/logical_design/decider_parser.rs:151

↓ 2 callersMethodinput_mut

(&mut self, colour: WireColour)

src/sim.rs:95

↓ 2 callersMethodis_arithmetic

(&self)

src/logical_design.rs:540

↓ 2 callersMethodis_cell_body

(&self)

src/checked_design.rs:248

↓ 2 callersMethodis_decider

(&self)

src/logical_design.rs:532

↓ 2 callersMethodis_memory

(&self)

src/checked_design.rs:191

↓ 2 callersMethodis_subset

(&self, other: &Self)

src/sim.rs:1673

↓ 2 callersMethodlast_time

(&self)

src/sim/vcd.rs:73

↓ 2 callersMethodlegalized

(&self)

src/phy/placement2.rs:487

↓ 2 callersFunctionlookup_str

(id: i32)

src/signal_lookup_table.rs:370

↓ 2 callersMethodmap_xy

(&self, func: F)

src/phy/placement2.rs:66

↓ 2 callersMethodmark_as_port

(&mut self, id: NodeId, direction: Direction, name: String, signal: Signal)

src/logical_design.rs:4362

↓ 2 callersMethodmemory_terminal_to_timing_boundary

(&self, terminal: &str)

src/mapped_design.rs:413

↓ 2 callersFunctionmethod_connect

(this: &Terminal, other: AnyUserData)

src/lua.rs:252

↓ 2 callersFunctionmethod_map_rtl

(rtl: &RTL)

src/lua.rs:419

↓ 2 callersMethodn_nodes

(&self)

src/phy/design.rs:225

↓ 2 callersFunctionnew

()

src/serializable_design.rs:635

↓ 2 callersMethodoutput_mut

(&mut self, colour: WireColour)

src/sim.rs:110

↓ 2 callersFunctionparser

()

src/logical_design/decider_parser.rs:33

↓ 2 callersFunctionprecedence

(op: &ArithmeticOperator)

src/logical_design/arithmetic_parser.rs:32

↓ 2 callersFunctionprint

()

src/tests/logical_design_tests.rs:1305

↓ 2 callersMethodprune

(&mut self, id: NodeId)

src/logical_design.rs:4515

↓ 2 callersFunctionrandom_01

(rng: &mut StdRng, p: f64)

src/phy/placement.rs:710

↓ 2 callersFunctionrect_attachment

(r: &RectData, attachment_index: u32)

src/svg.rs:706

↓ 2 callersMethodreset

(&mut self)

src/sim.rs:1368

↓ 2 callersMethodresolve_log_id

(&self, id: NodeId, log_id: usize)

src/lua/physical_ensemble.rs:24

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