Functions — github.com/ben-j-c/verilog2factorio

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Functions739 in github.com/ben-j-c/verilog2factorio

⨍ Functions 739◇ Types & classes 156

↓ 7 callersFunctionsimple

src/tests/lua.rs:6

↓ 6 callersMethodadd_dff

Create a standard D-Flip-Flop in this design. Returned NodeIds match the order of the function signature. Inputs are returned as wires, outputs are r

src/logical_design.rs:1051

↓ 6 callersMethodadd_line

( &mut self, x1: i32, y1: i32, x2: i32, y2: i32, colour: Option<String>, width: Option<i32>, )

↓ 6 callersMethodadd_neg

Add a combinator fitting the pattern that I call "negation". Equivalent to `!x` in Rust. Returns the id for that new combinator.

src/logical_design.rs:899

↓ 6 callersMethodadd_nop_simple

Add a combinator fitting the pattern that I call "no-operation". Converts the input signal to an output signal using an arithmetic combinator. Return

src/logical_design.rs:892

↓ 6 callersMethodadd_rom

( &mut self, ports: Vec<MemoryReadPort>, rom_values: Vec<i32>, density: Option<i32>, )

src/logical_design.rs:2720

↓ 6 callersMethodadd_sdffe

( &mut self, input: Signal, clk: Signal, srst: Signal, en: Signal, output: Signal, )

src/logical_design.rs:1388

↓ 6 callersMethodcenter_direction

(&self, other: &BBox)

src/phy/placement2.rs:43

↓ 6 callersMethodcheck_free_make_space

(&mut self, x: usize, y: usize, dimx: usize, dimy: usize)

src/phy/design.rs:2833

↓ 6 callersMethoddisconnect

(&mut self, send: NodeId, recv: NodeId)

src/checked_design.rs:453

↓ 6 callersFunctiondistance_diff

(a: &(f64, f64), b: &(f64, f64))

src/phy/design.rs:3033

↓ 6 callersMethodenergy_if_mov

( &self, id: Num, assignment: (Num, Num), connections_per_node: &Vec<Vec<usize>>, )

src/phy/placement.rs:947

↓ 6 callersMethodget_connected_combs

(&self, ldid: NodeId)

src/logical_design.rs:4206

↓ 6 callersMethodis_port

(&'a self, port_name: &str)

src/mapped_design.rs:602

↓ 6 callersMethodmut_node

(&mut self, id: NodeId)

src/logical_design.rs:3791

↓ 6 callersMethodpartial_cmp

(&self, other: &Self)

src/phy/route.rs:40

↓ 5 callersMethodadd_adffe

( &mut self, input: Signal, clk: Signal, en: Signal, arst: Signal, output: Signal, reset_value:

src/logical_design.rs:1307

↓ 5 callersMethodadd_latch

Inputs are returned as wires, outputs are retured as combinators. */ The returned tuple is (D wire id, CLK wire id, Output combinator id)

src/logical_design.rs:915

↓ 5 callersFunctionadd_signal_input_box_name_only

(ui: &mut egui::Ui, signal: &mut Signal, text: &mut String)

src/gui.rs:1173

↓ 5 callersMethodand

(&self, term: &Self)

src/logical_design/decider_parser.rs:106

↓ 5 callersMethodcheck_connections

src/checked_design.rs:2844

↓ 5 callersFunctioncoarsen_bit_ranges

Actually coarsen contiguous runs of bits that share the same driver I/O, same shift, or are constant, etc.

src/connected_design.rs:423

↓ 5 callersFunctiondraw_no_edge

( svg: &mut SVG, x: i32, y: i32, height: i32, corner_size: i32, colour: &str, level: i32, )

src/sim.rs:1541

↓ 5 callersMethodget_attached_nodes

(&self, nodeid: NodeId)

src/checked_design.rs:1420

↓ 5 callersMethodget_connectivity_as_vec_usize

(&self, ld: &LogicalDesign)

src/phy/design.rs:1828

↓ 5 callersFunctionget_large_logical_design

src/tests/logical_design_tests.rs:69

↓ 5 callersMethodis_constant

src/mapped_design.rs:72

↓ 5 callersFunctionlookup_id

(mapped_name: &str)

src/signal_lookup_table.rs:375

↓ 5 callersFunctionlookup_id_ignore_case

(mapped_name: &str)

src/signal_lookup_table.rs:385

↓ 5 callersMethodoutput

(&self, colour: WireColour)

↓ 5 callersMethodplace_new_comb

( &mut self, pos: (usize, usize), logical: &LogicalDesign, id: NodeId, )

src/phy/design.rs:2856

↓ 5 callersMethodprint_row

(&self, idx: usize)

src/sim.rs:1128

↓ 5 callersMethodprobe_green_out

(&self, id: NodeId)

↓ 5 callersMethodresolve_constant

src/serializable_design.rs:568

↓ 5 callersFunctionresolve_network

(val: (bool, bool))

src/serializable_design.rs:618

↓ 5 callersFunctionsignal_parser

src/logical_design/arithmetic_parser.rs:51

↓ 5 callersMethodunwrap_vec

src/checked_design.rs:320

↓ 4 callersMethodadd_wire_red_tie_inputs

It has the same behaviour as a wire in game. Attach the inputs of two combinators together. Returns the id for the wire you created.

src/logical_design.rs:3648

↓ 4 callersMethodadd_wire_red_tie_outputs

It has the same behaviour as a wire in game. Attach the outputs of two combinators together. Returns the id for the wire you created.

src/logical_design.rs:3641

↓ 4 callersMethodappend_description

(&mut self, nodeid: NodeId, description: &str)

src/logical_design.rs:3817

↓ 4 callersMethodcomplement

Logical complement of this operator.

src/logical_design.rs:98

↓ 4 callersFunctionconvert_connectivity_to_csr

(conn: &Vec<Vec<usize>>)

↓ 4 callersMethoddraw_placement

( &self, connections: &Vec<(usize, usize)>, _max_density: i32, filename: &str, )

src/phy/placement.rs:1005

↓ 4 callersMethodexecute_decider_output_signal_model

( &self, node: &Node, output_signals: &mut OutputState, network: (bool, bool), constant: Option<i32>

src/sim/decider_model.rs:55

↓ 4 callersMethodextract_combs

(&mut self, logical: &LogicalDesign)

src/phy/design.rs:314

↓ 4 callersMethodfor_all_cells

(&self, mut func: F)

src/mapped_design.rs:552

↓ 4 callersFunctionforce_insert_expressions

(des: &mut CheckedDesign, id: NodeId, ports: Range<usize>)

src/checked_design/checked_design_optimizations.rs:450

↓ 4 callersMethodget_cell_option

(&'a self, cell_name: &str)

src/mapped_design.rs:580

↓ 4 callersMethodget_colour

↓ 4 callersMethodget_decider_op

src/checked_design.rs:195

↓ 4 callersFunctionget_derivative_file_name

(filename: P, derivative: S)

↓ 4 callersFunctionget_lua

src/lua.rs:1349

↓ 4 callersMethodget_node_id

(&self, mapped_id: &String, terminal_name: &String)

src/connected_design.rs:353

↓ 4 callersMethodget_port_node

(&self, name: S)

src/logical_design.rs:4371

↓ 4 callersMethodget_seen_output_state

(&self, node: NodeId, colours: (bool, bool))

↓ 4 callersFunctionget_v2f_root

↓ 4 callersMethodget_wire_network

(&self, nodeid: NodeId)

src/logical_design.rs:4271

↓ 4 callersFunctionget_yosys_exe

↓ 4 callersMethodinto_bool_vec

src/mapped_design.rs:472

↓ 4 callersMethodis_wire_hub

↓ 4 callersMethodmake_chart

Generated by chatgpt

↓ 4 callersFunctionmethod_check_yosys

↓ 4 callersFunctionmethod_load_rtl

( filenames: &[P], top_mod: String, include_dir: Option<String>, )

↓ 4 callersFunctionmetis

(connectivity: &Vec<Vec<usize>>, n_parts: i32)

src/phy/partition.rs:251

↓ 4 callersMethodn_bits

src/connected_design.rs:55

↓ 4 callersMethodprobe_lamp_state

(&self, id: NodeId)

↓ 4 callersMethodrender_traces

↓ 4 callersFunctionruntime_err

↓ 4 callersMethodslide

( &mut self, assignment: (Num, Num), max_density: i32, negative_direction: bool, x_direction: bool,

src/phy/placement.rs:811

↓ 4 callersMethodunparse

src/logical_design.rs:4813

↓ 4 callersMethodunwrap_decider

src/logical_design.rs:259

↓ 4 callersMethodwidth

src/phy/design.rs:217

↓ 3 callersMethodadd_adff_isolated

( &mut self, input: Signal, clk: Signal, arst: Signal, output: Signal, reset_value: i32, negativ

src/logical_design.rs:1109

↓ 3 callersMethodadd_circle

( &mut self, cx: i32, cy: i32, r: i32, colour: (u8, u8, u8), label: Option<String>, hover: Optio

↓ 3 callersMethodadd_display_panel

src/logical_design.rs:3541

↓ 3 callersMethodadd_display_panel_entry

( &mut self, id: NodeId, left: Signal, operator: DeciderOperator, right: Signal, output: Signal,

src/logical_design.rs:3553

↓ 3 callersMethodadd_pmux

( &mut self, a: Option<Signal>, b: &[Signal], s: &[Signal], y: Signal, s_folded_expr: Option<&[Opt

src/logical_design.rs:1589

↓ 3 callersMethodadd_programmable_ram

( &mut self, arst: Signal, byte_select: Signal, read_ports: Vec<MemoryReadPort>, write_port: MemoryW

src/logical_design.rs:2056

↓ 3 callersMethodadd_wire_floating_red

See [`add_wire_red`]

src/logical_design.rs:3764

↓ 3 callersMethodadd_wire_red_on_input

(&mut self, comb: NodeId)

src/logical_design.rs:3652

↓ 3 callersMethodand_else_emplace

(&self, term: &Self)

src/logical_design/decider_parser.rs:118

↓ 3 callersMethodassert_is_not_wire_sum

(&self, id: NodeId)

src/logical_design.rs:3803

↓ 3 callersMethodbit

(&self, bit_number: usize)

src/connected_design.rs:48

↓ 3 callersMethodcomplement

src/logical_design/decider_parser.rs:133

↓ 3 callersFunctionconvert_to_signal_count

(var: &Option<Vec<Value>>)

src/sim.rs:1728

↓ 3 callersFunctiondraw_signal_level

( svg: &mut SVG, x: i32, y: i32, width: i32, height: i32, corner_size: i32, colour: &str, level: i32,

src/sim.rs:1521

↓ 3 callersFunctiondraw_transition_edge

( svg: &mut SVG, x: i32, y: i32, height: i32, corner_size: i32, colour: &str, level: i32, )

src/sim.rs:1502

↓ 3 callersMethodevaluate_decider_expressions

( &self, node: &Node, expressions: &Vec<(Signal, DeciderOperator, Signal)>, expression_conj_disj: &Vec

src/sim/decider_model.rs:150

↓ 3 callersMethodfanout_empty

Does this node not feed into any nodes?

src/logical_design.rs:519

↓ 3 callersMethodfor_all_top_level_io

(&self, mut func: F)

src/mapped_design.rs:535

↓ 3 callersMethodget_cell

(&'a self, cell_name: &str)

src/mapped_design.rs:569

↓ 3 callersMethodget_fanin_body_subgraphs

(&self, nodeid: NodeId)

src/checked_design.rs:2443

↓ 3 callersMethodget_logical

(&self, id: PhyId, logical: &'a LogicalDesign)

src/phy/design.rs:337

↓ 3 callersMethodget_neighbors

(&self, index: &SpaceIndex, _goal: &SpaceIndex)

src/phy/design.rs:2761

↓ 3 callersMethodget_seen_signal_count_any

(&self, node: NodeId, colours: (bool, bool))

↓ 3 callersFunctionget_simple_logical_design

src/tests/logical_design_tests.rs:22

↓ 3 callersMethodget_value

(&self, var: S, time: u64)

src/sim/vcd.rs:61

↓ 3 callersMethodinsert_nop_between

(&mut self, first: NodeId, second: NodeId)

src/checked_design.rs:1160

↓ 3 callersMethodis_driver

(&self, nodeid: NodeId, to_check: NodeId)

src/checked_design.rs:376

↓ 3 callersMethoditer_netnames

src/mapped_design.rs:624

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