| 1360 | } |
| 1361 | |
| 1362 | uint32_t |
| 1363 | ddr_target(int i) |
| 1364 | { |
| 1365 | uint32_t dev, rev; |
| 1366 | |
| 1367 | soc_id(&dev, &rev); |
| 1368 | if (dev == MV_DEV_88RC8180) { |
| 1369 | i = (ddr_sz_read(i) & 0xf0) >> 4; |
| 1370 | return (i == 0xe ? 0xc : |
| 1371 | (i == 0xd ? 0xd : |
| 1372 | (i == 0xb ? 0xe : |
| 1373 | (i == 0x7 ? 0xf : 0xc)))); |
| 1374 | } |
| 1375 | |
| 1376 | /* |
| 1377 | * On SOCs other than 88RC8180 Mbus unit ID for |
| 1378 | * DDR SDRAM controller is always 0x0. |
| 1379 | */ |
| 1380 | return (0); |
| 1381 | } |
| 1382 | |
| 1383 | /************************************************************************** |
| 1384 | * CESA windows routines |
no test coverage detected