* Set USB3 decode windows */
| 1556 | * Set USB3 decode windows |
| 1557 | */ |
| 1558 | static void |
| 1559 | decode_win_usb3_setup(u_long base) |
| 1560 | { |
| 1561 | uint32_t br, cr; |
| 1562 | int i, j; |
| 1563 | |
| 1564 | for (i = 0; i < MV_WIN_USB3_MAX; i++) { |
| 1565 | win_usb3_cr_write(base, i, 0); |
| 1566 | win_usb3_br_write(base, i, 0); |
| 1567 | } |
| 1568 | |
| 1569 | /* Only access to active DRAM banks is required */ |
| 1570 | for (i = 0; i < MV_WIN_DDR_MAX; i++) { |
| 1571 | if (ddr_is_active(i)) { |
| 1572 | br = ddr_base(i); |
| 1573 | cr = (((ddr_size(i) - 1) & |
| 1574 | (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | |
| 1575 | (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | |
| 1576 | (ddr_target(i) << IO_WIN_TGT_SHIFT) | |
| 1577 | IO_WIN_ENA_MASK); |
| 1578 | |
| 1579 | /* Set the first free USB3.0 window */ |
| 1580 | for (j = 0; j < MV_WIN_USB3_MAX; j++) { |
| 1581 | if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK) |
| 1582 | continue; |
| 1583 | |
| 1584 | win_usb3_br_write(base, j, br); |
| 1585 | win_usb3_cr_write(base, j, cr); |
| 1586 | break; |
| 1587 | } |
| 1588 | } |
| 1589 | } |
| 1590 | } |
| 1591 | |
| 1592 | /************************************************************************** |
| 1593 | * ETH windows routines |
nothing calls this directly
no test coverage detected