* Set CESA decode windows. */
| 1404 | * Set CESA decode windows. |
| 1405 | */ |
| 1406 | static void |
| 1407 | decode_win_cesa_setup(u_long base) |
| 1408 | { |
| 1409 | uint32_t br, cr; |
| 1410 | uint64_t size; |
| 1411 | int i, j; |
| 1412 | |
| 1413 | for (i = 0; i < MV_WIN_CESA_MAX; i++) { |
| 1414 | win_cesa_cr_write(base, i, 0); |
| 1415 | win_cesa_br_write(base, i, 0); |
| 1416 | } |
| 1417 | |
| 1418 | /* Only access to active DRAM banks is required */ |
| 1419 | for (i = 0; i < MV_WIN_DDR_MAX; i++) { |
| 1420 | if (ddr_is_active(i)) { |
| 1421 | br = ddr_base(i); |
| 1422 | |
| 1423 | size = ddr_size(i); |
| 1424 | /* |
| 1425 | * Armada 38x SoC's equipped with 4GB DRAM |
| 1426 | * suffer freeze during CESA operation, if |
| 1427 | * MBUS window opened at given DRAM CS reaches |
| 1428 | * end of the address space. Apply a workaround |
| 1429 | * by setting the window size to the closest possible |
| 1430 | * value, i.e. divide it by 2. |
| 1431 | */ |
| 1432 | if ((soc_family == MV_SOC_ARMADA_38X) && |
| 1433 | (size + ddr_base(i) == 0x100000000ULL)) |
| 1434 | size /= 2; |
| 1435 | |
| 1436 | cr = (((size - 1) & 0xffff0000) | |
| 1437 | (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | |
| 1438 | (ddr_target(i) << IO_WIN_TGT_SHIFT) | |
| 1439 | IO_WIN_ENA_MASK); |
| 1440 | |
| 1441 | /* Set the first free CESA window */ |
| 1442 | for (j = 0; j < MV_WIN_CESA_MAX; j++) { |
| 1443 | if (win_cesa_cr_read(base, j) & 0x1) |
| 1444 | continue; |
| 1445 | |
| 1446 | win_cesa_br_write(base, j, br); |
| 1447 | win_cesa_cr_write(base, j, cr); |
| 1448 | break; |
| 1449 | } |
| 1450 | } |
| 1451 | } |
| 1452 | } |
| 1453 | |
| 1454 | static void |
| 1455 | decode_win_a38x_cesa_setup(u_long base) |
no test coverage detected