* Set USB decode windows. */
| 1492 | * Set USB decode windows. |
| 1493 | */ |
| 1494 | static void |
| 1495 | decode_win_usb_setup(u_long base) |
| 1496 | { |
| 1497 | uint32_t br, cr; |
| 1498 | int i, j; |
| 1499 | |
| 1500 | if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port))) |
| 1501 | return; |
| 1502 | |
| 1503 | usb_port++; |
| 1504 | |
| 1505 | for (i = 0; i < MV_WIN_USB_MAX; i++) { |
| 1506 | win_usb_cr_write(base, i, 0); |
| 1507 | win_usb_br_write(base, i, 0); |
| 1508 | } |
| 1509 | |
| 1510 | /* Only access to active DRAM banks is required */ |
| 1511 | for (i = 0; i < MV_WIN_DDR_MAX; i++) { |
| 1512 | if (ddr_is_active(i)) { |
| 1513 | br = ddr_base(i); |
| 1514 | /* |
| 1515 | * XXX for 6281 we should handle Mbus write |
| 1516 | * burst limit field in the ctrl reg |
| 1517 | */ |
| 1518 | cr = (((ddr_size(i) - 1) & 0xffff0000) | |
| 1519 | (ddr_attr(i) << 8) | |
| 1520 | (ddr_target(i) << 4) | 1); |
| 1521 | |
| 1522 | /* Set the first free USB window */ |
| 1523 | for (j = 0; j < MV_WIN_USB_MAX; j++) { |
| 1524 | if (win_usb_cr_read(base, j) & 0x1) |
| 1525 | continue; |
| 1526 | |
| 1527 | win_usb_br_write(base, j, br); |
| 1528 | win_usb_cr_write(base, j, cr); |
| 1529 | break; |
| 1530 | } |
| 1531 | } |
| 1532 | } |
| 1533 | } |
| 1534 | |
| 1535 | /************************************************************************** |
| 1536 | * USB3 windows routines |
nothing calls this directly
no test coverage detected