* Configure AHCI decoding windows */
| 2402 | * Configure AHCI decoding windows |
| 2403 | */ |
| 2404 | static void |
| 2405 | decode_win_ahci_setup(u_long base) |
| 2406 | { |
| 2407 | uint32_t br, cr, sz; |
| 2408 | int i, j; |
| 2409 | |
| 2410 | for (i = 0; i < MV_WIN_SATA_MAX_ARMADA38X; i++) { |
| 2411 | win_sata_armada38x_cr_write(base, i, 0); |
| 2412 | win_sata_armada38x_br_write(base, i, 0); |
| 2413 | win_sata_armada38x_sz_write(base, i, 0); |
| 2414 | } |
| 2415 | |
| 2416 | for (i = 0; i < MV_WIN_DDR_MAX; i++) { |
| 2417 | if (ddr_is_active(i)) { |
| 2418 | cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | |
| 2419 | (ddr_target(i) << IO_WIN_TGT_SHIFT) | |
| 2420 | IO_WIN_ENA_MASK; |
| 2421 | br = ddr_base(i); |
| 2422 | sz = (ddr_size(i) - 1) & |
| 2423 | (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT); |
| 2424 | |
| 2425 | /* Use first available SATA window */ |
| 2426 | for (j = 0; j < MV_WIN_SATA_MAX_ARMADA38X; j++) { |
| 2427 | if (win_sata_armada38x_cr_read(base, j) & IO_WIN_ENA_MASK) |
| 2428 | continue; |
| 2429 | |
| 2430 | /* BASE is set to DRAM base (0x00000000) */ |
| 2431 | win_sata_armada38x_br_write(base, j, br); |
| 2432 | /* CTRL targets DRAM ctrl with 0x0E or 0x0D */ |
| 2433 | win_sata_armada38x_cr_write(base, j, cr); |
| 2434 | /* SIZE is set to 16MB - max value */ |
| 2435 | win_sata_armada38x_sz_write(base, j, sz); |
| 2436 | break; |
| 2437 | } |
| 2438 | } |
| 2439 | } |
| 2440 | } |
| 2441 | |
| 2442 | static void |
| 2443 | decode_win_ahci_dump(u_long base) |
nothing calls this directly
no test coverage detected