| 797 | } |
| 798 | |
| 799 | bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFunction& il, Instruction& instr, size_t addrSize, uint32_t decomposeFlags) |
| 800 | { |
| 801 | LowLevelILLabel trueLabel, falseLabel, doneLabel, dirFlagSet, dirFlagClear, dirFlagDone; |
| 802 | InstructionOperand& op1 = instr.operands[0]; |
| 803 | InstructionOperand& op2 = instr.operands[1]; |
| 804 | InstructionOperand& op3 = instr.operands[2]; |
| 805 | InstructionOperand& op4 = instr.operands[3]; |
| 806 | LowLevelILLabel trueCode, falseCode, again; |
| 807 | size_t registerSize = addrSize; |
| 808 | BNEndianness endian = arch->GetEndianness(); |
| 809 | switch (instr.operation) |
| 810 | { |
| 811 | case MIPS_ADD: |
| 812 | case MIPS_ADDU: |
| 813 | case MIPS_ADDI: |
| 814 | case MIPS_ADDIU: |
| 815 | if (op2.reg == REG_ZERO) |
| 816 | il.AddInstruction(SetRegisterOrNop(il, 4, registerSize, op1.reg, ReadILOperand(il, instr, 3, registerSize, 4))); |
| 817 | else |
| 818 | il.AddInstruction( |
| 819 | SetRegisterOrNop(il, 4, registerSize, op1.reg, |
| 820 | il.Add(4, |
| 821 | ReadILOperand(il, instr, 2, registerSize, 4), |
| 822 | ReadILOperand(il, instr, 3, registerSize, 4)))); |
| 823 | break; |
| 824 | case MIPS_DADD: |
| 825 | case MIPS_DADDU: |
| 826 | case MIPS_DADDI: |
| 827 | case MIPS_DADDIU: |
| 828 | if (op2.reg == REG_ZERO) |
| 829 | il.AddInstruction(SetRegisterOrNop(il, 8, registerSize, op1.reg, ReadILOperand(il, instr, 3, registerSize))); |
| 830 | else |
| 831 | il.AddInstruction( |
| 832 | SetRegisterOrNop(il, 8, registerSize, op1.reg, |
| 833 | il.Add(8, |
| 834 | ReadILOperand(il, instr, 2, registerSize), |
| 835 | ReadILOperand(il, instr, 3, registerSize)))); |
| 836 | break; |
| 837 | case MIPS_SUB: |
| 838 | case MIPS_SUBU: |
| 839 | il.AddInstruction(SetRegisterOrNop(il, 4, registerSize, op1.reg, |
| 840 | il.Sub(4, |
| 841 | ReadILOperand(il, instr, 2, registerSize, 4), |
| 842 | ReadILOperand(il, instr, 3, registerSize, 4)))); |
| 843 | break; |
| 844 | case MIPS_DSUB: |
| 845 | case MIPS_DSUBU: |
| 846 | il.AddInstruction(SetRegisterOrNop(il, 8, registerSize, op1.reg, |
| 847 | il.Sub(8, |
| 848 | ReadILOperand(il, instr, 2, registerSize, 8), |
| 849 | ReadILOperand(il, instr, 3, registerSize, 8)))); |
| 850 | break; |
| 851 | case MIPS_AND: |
| 852 | il.AddInstruction(SetRegisterOrNop(il, registerSize, registerSize, op1.reg, |
| 853 | il.And(registerSize, |
| 854 | ReadILOperand(il, instr, 2, registerSize), |
| 855 | ReadILOperand(il, instr, 3, registerSize)))); |
| 856 | break; |
no test coverage detected