| 681 | } |
| 682 | |
| 683 | static ExprId MoveFromCoprocessor(unsigned cop, LowLevelILFunction& il, size_t loadSize, uint32_t outReg, uint32_t reg, uint64_t sel, uint32_t decomposeFlags) |
| 684 | { |
| 685 | if (cop == 0) |
| 686 | { |
| 687 | Reg copReg = GetCop0Register(reg, sel); |
| 688 | if (copReg == REG_ZERO && IsCop0ImplementationDefined(reg, sel)) |
| 689 | { |
| 690 | if ((decomposeFlags & DECOMPOSE_FLAGS_CAVIUM) != 0) |
| 691 | { |
| 692 | copReg = GetCaviumCop0Register(reg, sel); |
| 693 | } |
| 694 | } |
| 695 | |
| 696 | if (copReg != REG_ZERO) |
| 697 | { |
| 698 | return il.Intrinsic( |
| 699 | {RegisterOrFlag::Register(outReg)}, |
| 700 | loadSize == 4 ? MIPS_INTRIN_MFC0 : MIPS_INTRIN_DMFC0, |
| 701 | {il.Register(loadSize, copReg)}); |
| 702 | |
| 703 | } |
| 704 | } |
| 705 | else if (cop == 2) |
| 706 | { |
| 707 | if ((decomposeFlags & DECOMPOSE_FLAGS_CAVIUM) != 0) |
| 708 | { |
| 709 | Reg cop2Reg = GetCaviumCop2Register(reg); |
| 710 | if (cop2Reg != REG_ZERO) |
| 711 | { |
| 712 | return il.Intrinsic( |
| 713 | {RegisterOrFlag::Register(outReg)}, |
| 714 | loadSize == 4 ? MIPS_INTRIN_MFC2 : MIPS_INTRIN_DMFC2, |
| 715 | {il.Register(loadSize, cop2Reg)}); |
| 716 | } |
| 717 | } |
| 718 | } |
| 719 | |
| 720 | return il.Intrinsic( |
| 721 | {RegisterOrFlag::Register(outReg)}, |
| 722 | loadSize == 4 ? MIPS_INTRIN_MFC_UNIMPLEMENTED : MIPS_INTRIN_DMFC_UNIMPLEMENTED, |
| 723 | {il.Const(4, cop), il.Const(4, reg), il.Const(4, sel)}); |
| 724 | } |
| 725 | |
| 726 | static ExprId MoveToCoprocessor(unsigned cop, LowLevelILFunction& il, size_t storeSize, uint32_t reg, uint64_t sel, ExprId srcExpr, uint32_t decomposeFlags) |
| 727 | { |
no test coverage detected