| 497 | } |
| 498 | |
| 499 | static Reg GetCaviumCop0Register(uint32_t reg, uint64_t sel) |
| 500 | { |
| 501 | switch (reg) |
| 502 | { |
| 503 | case 9: |
| 504 | switch (sel) |
| 505 | { |
| 506 | case 6: return CNREG0_CVM_COUNT; |
| 507 | case 7: return CNREG0_CVM_CTL; |
| 508 | default: return REG_ZERO; |
| 509 | } |
| 510 | break; |
| 511 | |
| 512 | case 11: |
| 513 | switch (sel) |
| 514 | { |
| 515 | case 6: return CNREG0_POWTHROTTLE; |
| 516 | case 7: return CNREG0_CVM_MEM_CTL; |
| 517 | default: return REG_ZERO; |
| 518 | } |
| 519 | break; |
| 520 | case 22: |
| 521 | switch (sel) |
| 522 | { |
| 523 | case 0: return CNREG0_MULTICORE_DBG; |
| 524 | default: return REG_ZERO; |
| 525 | } |
| 526 | break; |
| 527 | |
| 528 | default: return REG_ZERO; |
| 529 | } |
| 530 | } |
| 531 | |
| 532 | static Reg GetCaviumCop2Register(uint32_t reg) |
| 533 | { |
no outgoing calls
no test coverage detected