| 724 | } |
| 725 | |
| 726 | static ExprId MoveToCoprocessor(unsigned cop, LowLevelILFunction& il, size_t storeSize, uint32_t reg, uint64_t sel, ExprId srcExpr, uint32_t decomposeFlags) |
| 727 | { |
| 728 | if (cop == 0) |
| 729 | { |
| 730 | Reg copReg = GetCop0Register(reg, sel); |
| 731 | if (copReg == REG_ZERO && IsCop0ImplementationDefined(reg, sel)) |
| 732 | { |
| 733 | if ((decomposeFlags & DECOMPOSE_FLAGS_CAVIUM) != 0) |
| 734 | { |
| 735 | copReg = GetCaviumCop0Register(reg, sel); |
| 736 | } |
| 737 | } |
| 738 | |
| 739 | if (copReg != REG_ZERO) |
| 740 | { |
| 741 | return il.Intrinsic( |
| 742 | {}, |
| 743 | storeSize == 4 ? MIPS_INTRIN_MTC0 : MIPS_INTRIN_DMTC0, |
| 744 | {il.Register(storeSize, copReg), srcExpr}); |
| 745 | } |
| 746 | } |
| 747 | else if (cop == 2) |
| 748 | { |
| 749 | if ((decomposeFlags & DECOMPOSE_FLAGS_CAVIUM) != 0) |
| 750 | { |
| 751 | Reg cop2Reg = GetCaviumCop2Register(reg); |
| 752 | if (cop2Reg != REG_ZERO) |
| 753 | { |
| 754 | return il.Intrinsic( |
| 755 | {}, |
| 756 | storeSize == 4 ? MIPS_INTRIN_MTC2 : MIPS_INTRIN_DMTC2, |
| 757 | {il.Register(storeSize, cop2Reg), srcExpr}); |
| 758 | } |
| 759 | } |
| 760 | } |
| 761 | |
| 762 | return il.Intrinsic( |
| 763 | {}, |
| 764 | storeSize == 4 ? MIPS_INTRIN_MTC_UNIMPLEMENTED : MIPS_INTRIN_DMTC_UNIMPLEMENTED, |
| 765 | {il.Const(4, cop), il.Const(4, reg), il.Const(4, sel), srcExpr}); |
| 766 | } |
| 767 | |
| 768 | static ExprId SimpleIntrinsic(LowLevelILFunction& il, MipsIntrinsic intrinsic) |
| 769 | { |
no test coverage detected