Method GetInstructionLowLevelIL

arch/mips/arch_mips.cpp:498–755

	}

	virtual bool GetInstructionLowLevelIL(const uint8_t* data, uint64_t addr, size_t& len, LowLevelILFunction& il) override
	{
		Instruction instr, secondInstr;
		if (!Disassemble(data, addr, len, instr))
		{
			il.AddInstruction(il.Undefined());
			return false;
		}

		if (InstructionHasBranchDelay(instr) == 1)
		{
			if (len < 8)
			{
				LogWarn("Can not lift instruction with delay slot @ 0x%08" PRIx64, addr);
				return false;
			}

			if (!Disassemble(data + instr.size, addr + instr.size, len - instr.size, secondInstr))
			{
				il.AddInstruction(il.Undefined());
				return false;
			}

			bool status = true;
			bool isBranchLikely = InstructionIsBranchLikely(instr);
			if (isBranchLikely)
			{
				InstructionInfo instrInfo;
				LowLevelILLabel trueCode, falseCode;
				SetInstructionInfoForInstruction(addr, instr, instrInfo);
				il.AddInstruction(il.If(GetConditionForInstruction(il, instr, GetAddressSize()), trueCode, falseCode));
				il.MarkLabel(trueCode);
				il.SetCurrentAddress(this, addr + instr.size);
				GetLowLevelILForInstruction(this, addr + instr.size, il, secondInstr, GetAddressSize(), m_decomposeFlags);
				for (size_t i = 0; i < instrInfo.branchCount; i++)
				{
					if (instrInfo.branchType[i] == TrueBranch)
					{
						BNLowLevelILLabel* trueLabel = il.GetLabelForAddress(this, instrInfo.branchTarget[i]);
						if (trueLabel)
							il.AddInstruction(il.Goto(*trueLabel));
						else
							il.AddInstruction(il.Jump(il.ConstPointer(GetAddressSize(), instrInfo.branchTarget[i])));
						break;
					}
				}
				il.MarkLabel(falseCode);
			}
			else
			{
				size_t nop;

				// ensure we have space to preserve one register in case the delay slot
				// clobbers a value needed by the branch. this will be eliminated when
				// normal LLIL is generated from Lifted IL if we don't need it
				il.SetCurrentAddress(this, addr + instr.size);
				nop = il.Nop();
				il.AddInstruction(nop);