* Local Functions *******************************************************************************/ * Global initialization for all modes */

* Set MFIS CPU communication message register [i] G4MH[k] core to Cortex-A55 * CPU core(MFISAM[k]EMBR[i])(i=0-7)(k=0-1) * * Support only CPU 0 to G

* Set MFIS CPU communication message register [i] G4MH[k] core to Cortex-A55 * CPU core(MFISAM[k]EMBR[i])(i=0-7)(k=0-1) * * Support only CPU 0 to G

For reading SPR. */

-----------------------------------------------------------------------------------*/ Semaphore */

* Disable interrupts */

* Enable interrupts */

* tpl_filtering handles the filtering of messages. * It takes two data pointers (new_data and old_data), * If the check failed, tpl_filtering return

/ * Wait for NVM to become ready from busy state */

/ * @brief * Calculate prescaler value used to determine ADC clock. * * @details * The ADC clock is given by: HFPERCLK / (prescale + 1). * *

/ * @brief * Set clock divisor/prescaler. * * @note * If setting a LF clock prescaler, synchronization into the low frequency * domain is r

/ * @brief * Get HFRCO band in use. * * @return * HFRCO band in use. ************************************************************************

/ * @brief * Select PCNTn clock. * * @param[in] instance * PCNT instance number to set selected clock source for. * * @param[in] external *

* @brief Checks whether the specified DSI flag is set or not. * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instanc

/ * @brief * Optimize DCDC slice count based on the estimated average load current * in EM0 * * @param[in] em0LoadCurrent_mA * Estimated av

/ * @brief Select the micro SD card and wait for the card to become ready. * @return 1:Successful, 0:Timeout. **************************************

/ * @brief * Perform address phase of Flash write cycle. * @details * This function performs the address phase of a Flash write operation by *

\brief Get Interrupt Priority \details Reads the priority of an interrupt. The interrupt number can be positive to specify an external

* @brief Initializes the NVIC peripheral according to the specified * parameters in the NVIC_InitStruct. * @note To configure interrupt

/ * @brief * Wait for the QSPI to go into idle state. * * @param[in] qspi * Pointer to QSPI peripheral register block. **********************

* \brief This is the code that gets called on processor reset. * To initialize the device, and call the main() routine. */

/ * @brief * Get factory calibration value for a given peripheral register. * * @param[in] regAddress * Peripheral calibration register addr

/ * @brief * Get ultra low frequency RC oscillator clock frequency for target system. * * @note * This is an EFM32 proprietary function, not p

* @brief Sets the TIMx Input Capture 1 prescaler. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param

* @brief Sets the TIMx Input Capture 2 prescaler. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * periphera

/ * @brief * Configure USART operating in synchronous mode to use a given baudrate * (or as close as possible to specified baudrate). * * @det

/ * @brief * Reset USART/UART to same state as after a HW reset. * * @param[in] usart * Pointer to USART/UART peripheral register block. ****

\brief Count leading zeros This function counts the number of leading zeros of a data value. \param [in] value Value to count the leading

\brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, with

\brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that

* @brief C custom defined QADD for M3 and M0 processors */

* @brief C custom defined QSUB for M3 and M0 processors */

\brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a numbe