| 12470 | } |
| 12471 | |
| 12472 | void wait_cpu_cycle_write_ce020(uaecptr addr, int mode, uae_u32 v) |
| 12473 | { |
| 12474 | int ipl; |
| 12475 | |
| 12476 | sync_cycles(); |
| 12477 | |
| 12478 | x_do_cycles_pre(CYCLE_UNIT); |
| 12479 | |
| 12480 | blt_info.nasty_cnt = blt_info.blit_interrupt_trigger ? -0x7fffffff : 0; |
| 12481 | dma_cycle(&ipl); |
| 12482 | |
| 12483 | #ifdef DEBUGGER |
| 12484 | if (debug_dma) { |
| 12485 | int reg = 0x1100; |
| 12486 | if (mode < 0) |
| 12487 | reg |= 4; |
| 12488 | else if (mode > 0) |
| 12489 | reg |= 2; |
| 12490 | else |
| 12491 | reg |= 1; |
| 12492 | record_dma_write(reg, v, addr, DMARECORD_CPU, 1); |
| 12493 | } |
| 12494 | peekdma_data.mask = 0; |
| 12495 | #endif |
| 12496 | |
| 12497 | if (mode < 0) { |
| 12498 | put_long(addr, v); |
| 12499 | } else if (mode > 0) { |
| 12500 | put_word(addr, v); |
| 12501 | } else if (mode == 0) { |
| 12502 | put_byte(addr, v); |
| 12503 | } |
| 12504 | |
| 12505 | regs.chipset_latch_rw = regs.chipset_latch_write = v; |
| 12506 | |
| 12507 | x_do_cycles_post(CYCLE_UNIT, v); |
| 12508 | } |
| 12509 | |
| 12510 | void do_cycles_ce(int cycles) |
| 12511 | { |
no test coverage detected