| 9972 | } |
| 9973 | |
| 9974 | void mem_access_delay_long_write_c040 (uaecptr addr, uae_u32 v) |
| 9975 | { |
| 9976 | switch (ce_banktype[addr >> 16]) |
| 9977 | { |
| 9978 | case CE_MEMBANK_CHIP16: |
| 9979 | wait_cpu_cycle_write_ce020 (addr + 0, 1, (v >> 16) & 0xffff); |
| 9980 | wait_cpu_cycle_write_ce020 (addr + 2, 1, (v >> 0) & 0xffff); |
| 9981 | break; |
| 9982 | case CE_MEMBANK_CHIP32: |
| 9983 | if ((addr & 3) != 0) { |
| 9984 | wait_cpu_cycle_write_ce020 (addr + 0, 1, (v >> 16) & 0xffff); |
| 9985 | wait_cpu_cycle_write_ce020 (addr + 2, 1, (v >> 0) & 0xffff); |
| 9986 | } else { |
| 9987 | wait_cpu_cycle_write_ce020 (addr + 0, -1, v); |
| 9988 | } |
| 9989 | break; |
| 9990 | case CE_MEMBANK_FAST16: |
| 9991 | put_long (addr, v); |
| 9992 | do_cycles_c040_mem(1, v); |
| 9993 | break; |
| 9994 | case CE_MEMBANK_FAST32: |
| 9995 | put_long (addr, v); |
| 9996 | break; |
| 9997 | default: |
| 9998 | put_long (addr, v); |
| 9999 | break; |
| 10000 | } |
| 10001 | } |
| 10002 | |
| 10003 | static uae_u32 dcache040_get_data(uaecptr addr, struct cache040 *c, int line, int size) |
| 10004 | { |
nothing calls this directly
no test coverage detected