| 8973 | } |
| 8974 | |
| 8975 | void mem_access_delay_long_write_ce020 (uaecptr addr, uae_u32 v) |
| 8976 | { |
| 8977 | start_020_cycle(); |
| 8978 | switch (ce_banktype[addr >> 16]) |
| 8979 | { |
| 8980 | case CE_MEMBANK_CHIP16: |
| 8981 | wait_cpu_cycle_write_ce020 (addr + 0, 1, (v >> 16) & 0xffff); |
| 8982 | wait_cpu_cycle_write_ce020 (addr + 2, 1, (v >> 0) & 0xffff); |
| 8983 | break; |
| 8984 | case CE_MEMBANK_CHIP32: |
| 8985 | if ((addr & 3) != 0) { |
| 8986 | wait_cpu_cycle_write_ce020 (addr + 0, 1, (v >> 16) & 0xffff); |
| 8987 | wait_cpu_cycle_write_ce020 (addr + 2, 1, (v >> 0) & 0xffff); |
| 8988 | } else { |
| 8989 | wait_cpu_cycle_write_ce020 (addr + 0, -1, v); |
| 8990 | } |
| 8991 | break; |
| 8992 | case CE_MEMBANK_FAST32: |
| 8993 | put_long (addr, v); |
| 8994 | if ((addr & 3) != 0) |
| 8995 | do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v); |
| 8996 | else |
| 8997 | do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v); |
| 8998 | break; |
| 8999 | case CE_MEMBANK_FAST16: |
| 9000 | put_long (addr, v); |
| 9001 | do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v); |
| 9002 | break; |
| 9003 | default: |
| 9004 | put_long (addr, v); |
| 9005 | break; |
| 9006 | } |
| 9007 | end_020_cycle(); |
| 9008 | } |
| 9009 | |
| 9010 | |
| 9011 | // 68030 caches aren't so simple as 68020 cache.. |
no test coverage detected