| 3605 | } |
| 3606 | |
| 3607 | static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn, |
| 3608 | uint64_t Address, const void *Decoder) |
| 3609 | { |
| 3610 | DecodeStatus S = MCDisassembler_Success; |
| 3611 | unsigned addrmode; |
| 3612 | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
| 3613 | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
| 3614 | bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); |
| 3615 | bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); |
| 3616 | |
| 3617 | if (Rn == 15) { |
| 3618 | switch (MCInst_getOpcode(Inst)) { |
| 3619 | case ARM_t2LDRBs: |
| 3620 | MCInst_setOpcode(Inst, ARM_t2LDRBpci); |
| 3621 | break; |
| 3622 | case ARM_t2LDRHs: |
| 3623 | MCInst_setOpcode(Inst, ARM_t2LDRHpci); |
| 3624 | break; |
| 3625 | case ARM_t2LDRSHs: |
| 3626 | MCInst_setOpcode(Inst, ARM_t2LDRSHpci); |
| 3627 | break; |
| 3628 | case ARM_t2LDRSBs: |
| 3629 | MCInst_setOpcode(Inst, ARM_t2LDRSBpci); |
| 3630 | break; |
| 3631 | case ARM_t2LDRs: |
| 3632 | MCInst_setOpcode(Inst, ARM_t2LDRpci); |
| 3633 | break; |
| 3634 | case ARM_t2PLDs: |
| 3635 | MCInst_setOpcode(Inst, ARM_t2PLDpci); |
| 3636 | break; |
| 3637 | case ARM_t2PLIs: |
| 3638 | MCInst_setOpcode(Inst, ARM_t2PLIpci); |
| 3639 | break; |
| 3640 | default: |
| 3641 | return MCDisassembler_Fail; |
| 3642 | } |
| 3643 | |
| 3644 | return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); |
| 3645 | } |
| 3646 | |
| 3647 | if (Rt == 15) { |
| 3648 | switch (MCInst_getOpcode(Inst)) { |
| 3649 | case ARM_t2LDRSHs: |
| 3650 | return MCDisassembler_Fail; |
| 3651 | case ARM_t2LDRHs: |
| 3652 | MCInst_setOpcode(Inst, ARM_t2PLDWs); |
| 3653 | break; |
| 3654 | case ARM_t2LDRSBs: |
| 3655 | MCInst_setOpcode(Inst, ARM_t2PLIs); |
| 3656 | default: |
| 3657 | break; |
| 3658 | } |
| 3659 | } |
| 3660 | |
| 3661 | switch (MCInst_getOpcode(Inst)) { |
| 3662 | case ARM_t2PLDs: |
| 3663 | break; |
| 3664 | case ARM_t2PLIs: |
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