| 191 | } |
| 192 | |
| 193 | static ExprId GetShiftedRegister( |
| 194 | LowLevelILFunction& il, InstructionOperand& operand, size_t regNum, size_t resultSize) |
| 195 | { |
| 196 | ExprId res; |
| 197 | |
| 198 | // peel off the variants that return early |
| 199 | switch (operand.shiftType) |
| 200 | { |
| 201 | case ShiftType_NONE: |
| 202 | res = ExtractRegister(il, operand, regNum, REGSZ_O(operand), false, resultSize); |
| 203 | return res; |
| 204 | case ShiftType_ASR: |
| 205 | res = ExtractRegister(il, operand, regNum, REGSZ_O(operand), false, resultSize); |
| 206 | if (operand.shiftValue) |
| 207 | res = il.ArithShiftRight(resultSize, res, il.Const(1, operand.shiftValue)); |
| 208 | return res; |
| 209 | case ShiftType_LSR: |
| 210 | res = ExtractRegister(il, operand, regNum, REGSZ_O(operand), false, resultSize); |
| 211 | if (operand.shiftValue) |
| 212 | res = il.LogicalShiftRight(resultSize, res, il.Const(1, operand.shiftValue)); |
| 213 | return res; |
| 214 | case ShiftType_ROR: |
| 215 | res = ExtractRegister(il, operand, regNum, REGSZ_O(operand), false, resultSize); |
| 216 | if (operand.shiftValue) |
| 217 | res = il.RotateRight(resultSize, res, il.Const(1, operand.shiftValue)); |
| 218 | return res; |
| 219 | default: |
| 220 | break; |
| 221 | } |
| 222 | |
| 223 | // everything else falls through to maybe be left shifted |
| 224 | switch (operand.shiftType) |
| 225 | { |
| 226 | case ShiftType_LSL: |
| 227 | res = ExtractRegister(il, operand, regNum, REGSZ_O(operand), false, resultSize); |
| 228 | break; |
| 229 | case ShiftType_SXTB: |
| 230 | res = ExtractRegister(il, operand, regNum, 1, true, resultSize); |
| 231 | break; |
| 232 | case ShiftType_SXTH: |
| 233 | res = ExtractRegister(il, operand, regNum, 2, true, resultSize); |
| 234 | break; |
| 235 | case ShiftType_SXTW: |
| 236 | res = ExtractRegister(il, operand, regNum, 4, true, resultSize); |
| 237 | break; |
| 238 | case ShiftType_SXTX: |
| 239 | res = ExtractRegister(il, operand, regNum, 8, true, resultSize); |
| 240 | break; |
| 241 | case ShiftType_UXTB: |
| 242 | res = ExtractRegister(il, operand, regNum, 1, false, resultSize); |
| 243 | break; |
| 244 | case ShiftType_UXTH: |
| 245 | res = ExtractRegister(il, operand, regNum, 2, false, resultSize); |
| 246 | break; |
| 247 | case ShiftType_UXTW: |
| 248 | res = ExtractRegister(il, operand, regNum, 4, false, resultSize); |
| 249 | break; |
| 250 | case ShiftType_UXTX: |
no test coverage detected