| 359 | |
| 360 | |
| 361 | static size_t ReadILOperand(LowLevelILFunction& il, InstructionOperand& operand, size_t resultSize) |
| 362 | { |
| 363 | switch (operand.operandClass) |
| 364 | { |
| 365 | case IMM32: |
| 366 | case IMM64: |
| 367 | if (operand.shiftType != ShiftType_NONE && operand.shiftValue) |
| 368 | return il.Const(resultSize, operand.immediate << operand.shiftValue); |
| 369 | else |
| 370 | return il.Const(resultSize, operand.immediate); |
| 371 | case LABEL: |
| 372 | return il.ConstPointer(8, operand.immediate); |
| 373 | case REG: |
| 374 | if (IS_ZERO_REG(operand.reg[0])) |
| 375 | return il.Const(resultSize, 0); |
| 376 | return GetShiftedRegister(il, operand, 0, resultSize); |
| 377 | case MEM_REG: |
| 378 | return il.Load(resultSize, il.Register(8, operand.reg[0])); |
| 379 | case MEM_OFFSET: |
| 380 | if (operand.immediate != 0) |
| 381 | return il.Load( |
| 382 | resultSize, il.Add(8, il.Register(8, operand.reg[0]), il.Const(8, operand.immediate))); |
| 383 | else |
| 384 | return il.Load(resultSize, il.Register(8, operand.reg[0])); |
| 385 | case MEM_EXTENDED: |
| 386 | return il.Load(resultSize, GetILOperandEffectiveAddress(il, operand, resultSize, NONE, 0)); |
| 387 | case MEM_PRE_IDX: |
| 388 | case MEM_POST_IDX: |
| 389 | case MULTI_REG: |
| 390 | case FIMM32: |
| 391 | return GetFloat(il, operand, resultSize); |
| 392 | case NONE: |
| 393 | default: |
| 394 | return il.Unimplemented(); |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | unsigned v_unpack_lookup_sz[15] = {0, 1, 2, 4, 8, 16, 1, 2, 4, 8, 1, 2, 4, 1, 1}; |
| 399 |
no test coverage detected