| 887 | } |
| 888 | |
| 889 | static void LoadStoreOperand(LowLevelILFunction& il, bool load, |
| 890 | InstructionOperand& operand1, /* register that gets read/written */ |
| 891 | InstructionOperand& operand2, /* location the read/write occurs */ |
| 892 | int load_store_sz) |
| 893 | { |
| 894 | if (!load_store_sz) |
| 895 | load_store_sz = REGSZ_O(operand1); |
| 896 | |
| 897 | ExprId tmp; |
| 898 | if (load) |
| 899 | { |
| 900 | switch (operand2.operandClass) |
| 901 | { |
| 902 | case MEM_REG: |
| 903 | // operand1.reg = [operand2.reg] |
| 904 | il.AddInstruction( |
| 905 | ILSETREG_O(operand1, il.Operand(1, il.Load(load_store_sz, ILREG_O(operand2))))); |
| 906 | break; |
| 907 | case MEM_OFFSET: |
| 908 | if (!load_store_sz) |
| 909 | load_store_sz = REGSZ_O(operand1); |
| 910 | |
| 911 | // operand1.reg = [operand2.reg + operand2.imm] |
| 912 | if (IMM_O(operand2) == 0) |
| 913 | tmp = ILREG_O(operand2); |
| 914 | else |
| 915 | tmp = ILADDREG_O(operand2, il.Const(REGSZ_O(operand2), IMM_O(operand2))); |
| 916 | |
| 917 | il.AddInstruction(ILSETREG_O(operand1, il.Operand(1, il.Load(load_store_sz, tmp)))); |
| 918 | break; |
| 919 | case MEM_PRE_IDX: |
| 920 | // operand2.reg += operand2.imm |
| 921 | if (IMM_O(operand2) != 0) |
| 922 | il.AddInstruction(ILSETREG_O(operand2, il.Add(REGSZ_O(operand2), ILREG_O(operand2), |
| 923 | il.Const(REGSZ_O(operand2), IMM_O(operand2))))); |
| 924 | // operand1.reg = [operand2.reg] |
| 925 | il.AddInstruction( |
| 926 | ILSETREG_O(operand1, il.Operand(1, il.Load(load_store_sz, ILREG_O(operand2))))); |
| 927 | break; |
| 928 | case MEM_POST_IDX: |
| 929 | // operand1.reg = [operand2.reg] |
| 930 | il.AddInstruction( |
| 931 | ILSETREG_O(operand1, il.Operand(1, il.Load(load_store_sz, ILREG_O(operand2))))); |
| 932 | // operand2.reg += operand2.imm |
| 933 | if (IMM_O(operand2) != 0) |
| 934 | il.AddInstruction(ILSETREG_O(operand2, il.Add(REGSZ_O(operand2), ILREG_O(operand2), |
| 935 | il.Const(REGSZ_O(operand2), IMM_O(operand2))))); |
| 936 | break; |
| 937 | case MEM_EXTENDED: |
| 938 | il.AddInstruction(ILSETREG_O(operand1, |
| 939 | il.Operand(1, il.Load(load_store_sz, |
| 940 | il.Add(REGSZ_O(operand2), ILREG_O(operand2), |
| 941 | GetShiftedRegister(il, operand2, 1, REGSZ_O(operand2))))))); |
| 942 | break; |
| 943 | case LABEL: |
| 944 | il.AddInstruction(ILSETREG_O( |
| 945 | operand1, il.Operand(1, il.Load(load_store_sz, il.ConstPointer(8, IMM_O(operand2)))))); |
| 946 | break; |
no test coverage detected