| 556 | } |
| 557 | |
| 558 | static int arm_gicv3_wait_rwp(rt_uint64_t index, rt_uint64_t irq) |
| 559 | { |
| 560 | rt_uint64_t rwp_bit; |
| 561 | rt_uint64_t base; |
| 562 | |
| 563 | RT_ASSERT(index < ARM_GIC_MAX_NR); |
| 564 | |
| 565 | if (irq < 32) |
| 566 | { |
| 567 | rt_int32_t cpu_id = rt_hw_cpu_id(); |
| 568 | |
| 569 | base = _gic_table[index].redist_hw_base[cpu_id]; |
| 570 | rwp_bit = GICR_CTLR_RWP; |
| 571 | } |
| 572 | else |
| 573 | { |
| 574 | base = _gic_table[index].dist_hw_base; |
| 575 | rwp_bit = GICD_CTLR_RWP; |
| 576 | } |
| 577 | |
| 578 | while (HWREG32(base) & rwp_bit) |
| 579 | { |
| 580 | } |
| 581 | |
| 582 | return 0; |
| 583 | } |
| 584 | |
| 585 | int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start) |
| 586 | { |
no test coverage detected