| 685 | } |
| 686 | |
| 687 | int arm_gic_redist_init(rt_uint64_t index, rt_uint64_t redist_base) |
| 688 | { |
| 689 | int i; |
| 690 | int cpu_id = rt_hw_cpu_id(); |
| 691 | static int master_cpu_id = -1; |
| 692 | |
| 693 | RT_ASSERT(index < ARM_GIC_MAX_NR); |
| 694 | |
| 695 | if (master_cpu_id < 0) |
| 696 | { |
| 697 | master_cpu_id = 0; |
| 698 | rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, &master_cpu_id, sizeof(master_cpu_id)); |
| 699 | } |
| 700 | |
| 701 | if (!_gic_table[index].redist_hw_base[master_cpu_id]) |
| 702 | { |
| 703 | _gic_table[index].redist_hw_base[master_cpu_id] = redist_base; |
| 704 | } |
| 705 | redist_base = _gic_table[index].redist_hw_base[master_cpu_id]; |
| 706 | |
| 707 | redist_base += cpu_id * (2 << 16); |
| 708 | _gic_table[index].redist_hw_base[cpu_id] = redist_base; |
| 709 | |
| 710 | /* redistributor enable */ |
| 711 | GIC_RDIST_WAKER(redist_base) &= ~(1 << 1); |
| 712 | while (GIC_RDIST_WAKER(redist_base) & (1 << 2)) |
| 713 | { |
| 714 | } |
| 715 | |
| 716 | /* Disable all sgi and ppi interrupt */ |
| 717 | GIC_RDISTSGI_ICENABLER0(redist_base) = 0xffffffff; |
| 718 | arm_gicv3_wait_rwp(0, 0); |
| 719 | |
| 720 | /* Clear all inetrrupt pending */ |
| 721 | GIC_RDISTSGI_ICPENDR0(redist_base) = 0xffffffff; |
| 722 | |
| 723 | /* the corresponding interrupt is Group 1 or Non-secure Group 1. */ |
| 724 | GIC_RDISTSGI_IGROUPR0(redist_base, 0) = 0xffffffff; |
| 725 | GIC_RDISTSGI_IGRPMODR0(redist_base, 0) = 0xffffffff; |
| 726 | |
| 727 | /* Configure default priorities for SGI 0:15 and PPI 16:31. */ |
| 728 | for (i = 0; i < 32; i += 4) |
| 729 | { |
| 730 | GIC_RDISTSGI_IPRIORITYR(redist_base, i) = 0xa0a0a0a0U; |
| 731 | } |
| 732 | |
| 733 | /* Trigger level for PPI interrupts*/ |
| 734 | GIC_RDISTSGI_ICFGR1(redist_base) = 0; |
| 735 | return 0; |
| 736 | } |
| 737 | |
| 738 | int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base) |
| 739 | { |
no test coverage detected