| 583 | } |
| 584 | |
| 585 | int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start) |
| 586 | { |
| 587 | int i; |
| 588 | unsigned int gic_type; |
| 589 | rt_uint64_t main_cpu_affinity_val; |
| 590 | |
| 591 | RT_UNUSED(i); |
| 592 | RT_UNUSED(main_cpu_affinity_val); |
| 593 | RT_ASSERT(index < ARM_GIC_MAX_NR); |
| 594 | |
| 595 | _gic_table[index].dist_hw_base = dist_base; |
| 596 | _gic_table[index].offset = irq_start; |
| 597 | |
| 598 | |
| 599 | /* Find out how many interrupts are supported. */ |
| 600 | gic_type = GIC_DIST_TYPE(dist_base); |
| 601 | _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; |
| 602 | |
| 603 | /* |
| 604 | * The GIC only supports up to 1020 interrupt sources. |
| 605 | * Limit this to either the architected maximum, or the |
| 606 | * platform maximum. |
| 607 | */ |
| 608 | if (_gic_max_irq > 1020) |
| 609 | { |
| 610 | _gic_max_irq = 1020; |
| 611 | } |
| 612 | if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ |
| 613 | { |
| 614 | _gic_max_irq = ARM_GIC_NR_IRQS; |
| 615 | } |
| 616 | |
| 617 | #ifndef RT_AMP_SLAVE |
| 618 | |
| 619 | GIC_DIST_CTRL(dist_base) = 0; |
| 620 | /* Wait for register write pending */ |
| 621 | arm_gicv3_wait_rwp(0, 32); |
| 622 | |
| 623 | /* Set all global interrupts to be level triggered, active low. */ |
| 624 | for (i = 32; i < _gic_max_irq; i += 16) |
| 625 | { |
| 626 | GIC_DIST_CONFIG(dist_base, i) = 0; |
| 627 | } |
| 628 | |
| 629 | arm_gicv3_wait_rwp(0, 32); |
| 630 | |
| 631 | #ifdef RT_USING_SMP |
| 632 | main_cpu_affinity_val = rt_cpu_mpidr_table[ARM_SPI_BIND_CPU_ID]; |
| 633 | #else |
| 634 | __asm__ volatile ("mrs %0, mpidr_el1":"=r"(main_cpu_affinity_val)); |
| 635 | #endif |
| 636 | |
| 637 | /* aff3[39:32], aff2[23:16], aff1[15:8], aff0[7:0] */ |
| 638 | main_cpu_affinity_val &= 0xff00ffffffULL; |
| 639 | |
| 640 | /* Set all global interrupts to this CPU only. */ |
| 641 | for (i = 32; i < _gic_max_irq; i++) |
| 642 | { |
nothing calls this directly
no test coverage detected