| 879 | } |
| 880 | |
| 881 | rt_ssize_t rt_pci_msix_enable_range_affinity(struct rt_pci_device *pdev, |
| 882 | struct rt_pci_msix_entry *entries, int min, int max, |
| 883 | RT_IRQ_AFFINITY_DECLARE((*affinities))) |
| 884 | { |
| 885 | int nvec = max; |
| 886 | rt_size_t entries_nr; |
| 887 | |
| 888 | if (!pdev || min > max) |
| 889 | { |
| 890 | return -RT_EINVAL; |
| 891 | } |
| 892 | |
| 893 | if (pdev->no_msi) |
| 894 | { |
| 895 | return -RT_ENOSYS; |
| 896 | } |
| 897 | |
| 898 | if (!pdev->msi_pic) |
| 899 | { |
| 900 | return -RT_ENOSYS; |
| 901 | } |
| 902 | |
| 903 | if (pdev->msix_enabled) |
| 904 | { |
| 905 | LOG_W("%s: MSI-X is enabled", rt_dm_dev_get_name(&pdev->parent)); |
| 906 | |
| 907 | return -RT_EINVAL; |
| 908 | } |
| 909 | |
| 910 | entries_nr = rt_pci_msix_vector_count(pdev); |
| 911 | |
| 912 | if (entries_nr < 0) |
| 913 | { |
| 914 | return entries_nr; |
| 915 | } |
| 916 | |
| 917 | if (nvec > entries_nr) |
| 918 | { |
| 919 | return -RT_EEMPTY; |
| 920 | } |
| 921 | |
| 922 | if (!entries) |
| 923 | { |
| 924 | return 0; |
| 925 | } |
| 926 | |
| 927 | /* Check if entries is valid */ |
| 928 | for (int i = 0; i < nvec; ++i) |
| 929 | { |
| 930 | struct rt_pci_msix_entry *target = &entries[i]; |
| 931 | |
| 932 | if (target->index >= entries_nr) |
| 933 | { |
| 934 | return -RT_EINVAL; |
| 935 | } |
| 936 | |
| 937 | for (int j = i + 1; j < nvec; ++j) |
| 938 | { |
no test coverage detected