| 789 | } |
| 790 | |
| 791 | static rt_ssize_t msix_capability_init(struct rt_pci_device *pdev, |
| 792 | struct rt_pci_msix_entry *entries, int nvec, |
| 793 | RT_IRQ_AFFINITY_DECLARE((*affinities))) |
| 794 | { |
| 795 | rt_err_t err; |
| 796 | rt_uint16_t msgctl; |
| 797 | rt_size_t table_size; |
| 798 | void *table_base, *table_entry; |
| 799 | struct rt_pci_msi_desc *desc; |
| 800 | struct rt_pci_msix_entry *entry; |
| 801 | |
| 802 | /* |
| 803 | * Some devices require MSI-X to be enabled before the MSI-X |
| 804 | * registers can be accessed. |
| 805 | * Mask all the vectors to prevent interrupts coming in before |
| 806 | * they're fully set up. |
| 807 | */ |
| 808 | msix_update_ctrl(pdev, 0, PCIM_MSIXCTRL_FUNCTION_MASK | PCIM_MSIXCTRL_MSIX_ENABLE); |
| 809 | |
| 810 | rt_pci_read_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, &msgctl); |
| 811 | /* Request & Map MSI-X table region */ |
| 812 | table_size = rt_pci_msix_table_size(msgctl); |
| 813 | table_base = msix_table_remap(pdev, table_size); |
| 814 | |
| 815 | if (!table_base) |
| 816 | { |
| 817 | LOG_E("%s: Remap MSI-X table fail", rt_dm_dev_get_name(&pdev->parent)); |
| 818 | |
| 819 | err = -RT_ENOMEM; |
| 820 | goto _out_disbale_msix; |
| 821 | } |
| 822 | |
| 823 | pdev->msix_base = table_base; |
| 824 | |
| 825 | spin_lock(&pdev->msi_lock); |
| 826 | |
| 827 | if (!(err = msix_setup_msi_descs(pdev, table_base, entries, nvec))) |
| 828 | { |
| 829 | if (!(err = rt_pci_msi_setup_irqs(pdev, nvec, PCIY_MSIX))) |
| 830 | { |
| 831 | /* Check if all MSI entries honor device restrictions */ |
| 832 | err = msi_verify_entries(pdev); |
| 833 | } |
| 834 | } |
| 835 | |
| 836 | spin_unlock(&pdev->msi_lock); |
| 837 | |
| 838 | if (err) |
| 839 | { |
| 840 | rt_pci_msi_free_irqs(pdev); |
| 841 | |
| 842 | LOG_E("%s: Setup %s interrupts(%d) error = %s", |
| 843 | rt_dm_dev_get_name(&pdev->parent), "MSI-X", nvec, rt_strerror(err)); |
| 844 | |
| 845 | goto _out_disbale_msix; |
| 846 | } |
| 847 | |
| 848 | entry = entries; |
no test coverage detected