| 735 | } |
| 736 | |
| 737 | static void *msix_table_remap(struct rt_pci_device *pdev, rt_size_t entries_nr) |
| 738 | { |
| 739 | rt_uint8_t bir; |
| 740 | rt_uint32_t table_offset; |
| 741 | rt_ubase_t table_base_phys; |
| 742 | |
| 743 | rt_pci_read_config_u32(pdev, pdev->msix_cap + PCIR_MSIX_TABLE, &table_offset); |
| 744 | bir = (rt_uint8_t)(table_offset & PCIM_MSIX_BIR_MASK); |
| 745 | |
| 746 | if (pdev->resource[bir].flags & PCI_BUS_REGION_F_NONE) |
| 747 | { |
| 748 | LOG_E("%s: BAR[bir = %d] is invalid", rt_dm_dev_get_name(&pdev->parent), bir); |
| 749 | |
| 750 | return RT_NULL; |
| 751 | } |
| 752 | |
| 753 | table_base_phys = pdev->resource[bir].base + (table_offset & ~PCIM_MSIX_BIR_MASK); |
| 754 | |
| 755 | return rt_ioremap((void *)table_base_phys, entries_nr * PCIM_MSIX_ENTRY_SIZE); |
| 756 | } |
| 757 | |
| 758 | static rt_err_t msix_setup_msi_descs(struct rt_pci_device *pdev, |
| 759 | void *table_base, struct rt_pci_msix_entry *entries, int nvec) |
no test coverage detected