| 539 | } |
| 540 | |
| 541 | void SpeedWrite(u32 addr, u16 value, int width) |
| 542 | { |
| 543 | switch (addr) |
| 544 | { |
| 545 | case 0x10000020: |
| 546 | // DevCon.WriteLn("DEV9: SPD_R_20 %dbit write %x", wisth, value); |
| 547 | return; |
| 548 | case SPD_R_INTR_STAT: |
| 549 | Console.Error("DEV9: SPD_R_INTR_STAT %dbit write, WTF? %x", width, value); |
| 550 | dev9.irqcause = value; |
| 551 | return; |
| 552 | case SPD_R_INTR_MASK: // 8bit writes affect whole reg |
| 553 | //DevCon.WriteLn("DEV9: SPD_R_INTR_MASK %dbit write %x", checking for masked/unmasked interrupts", width, value); |
| 554 | if ((dev9.irqmask != value) && ((dev9.irqmask | value) & dev9.irqcause)) |
| 555 | { |
| 556 | //DevCon.WriteLn("DEV9: SPD_R_INTR_MASK firing unmasked interrupts"); |
| 557 | dev9Irq(1); |
| 558 | } |
| 559 | dev9.irqmask = value; |
| 560 | return; |
| 561 | |
| 562 | case SPD_R_PIO_DIR: |
| 563 | DevCon.WriteLn("DEV9: SPD_R_PIO_DIR %dbit write %x", width, value); |
| 564 | |
| 565 | if ((value & 0xc0) != 0xc0) |
| 566 | return; |
| 567 | |
| 568 | if ((value & 0x30) == 0x20) |
| 569 | { |
| 570 | dev9.eeprom_state = 0; |
| 571 | } |
| 572 | dev9.eeprom_dir = (value >> 4) & 3; |
| 573 | return; |
| 574 | |
| 575 | case SPD_R_PIO_DATA: |
| 576 | //DevCon.WriteLn("DEV9: SPD_R_PIO_DATA %dbit write %x", width, value); |
| 577 | |
| 578 | if ((value & 0xc0) != 0xc0) |
| 579 | return; |
| 580 | |
| 581 | switch (dev9.eeprom_state) |
| 582 | { |
| 583 | case EEPROM_READY: |
| 584 | dev9.eeprom_command = 0; |
| 585 | dev9.eeprom_state++; |
| 586 | break; |
| 587 | case EEPROM_OPCD0: |
| 588 | dev9.eeprom_command = (value >> 4) & 2; |
| 589 | dev9.eeprom_state++; |
| 590 | dev9.eeprom_bit = 0xFF; |
| 591 | break; |
| 592 | case EEPROM_OPCD1: |
| 593 | dev9.eeprom_command |= (value >> 5) & 1; |
| 594 | dev9.eeprom_state++; |
| 595 | break; |
| 596 | case EEPROM_ADDR0: |
| 597 | case EEPROM_ADDR1: |
| 598 | case EEPROM_ADDR2: |
no test coverage detected