FIFO counters operate based on the direction set in SPD_R_XFR_CTRL Both might have to set to the same direction for (SPEED <-> HDD) to work
| 388 | // FIFO counters operate based on the direction set in SPD_R_XFR_CTRL |
| 389 | // Both might have to set to the same direction for (SPEED <-> HDD) to work |
| 390 | void DEV9runFIFO() |
| 391 | { |
| 392 | const bool iopWrite = dev9.xfr_ctrl & SPD_XFR_WRITE; // IOP writes to FIFO |
| 393 | const bool hddRead = dev9.if_ctrl & SPD_IF_READ; // HDD writes to FIFO |
| 394 | |
| 395 | const bool iopXfer = (dev9.dma_iop_ptr != nullptr) && (dev9.xfr_ctrl & SPD_XFR_DMAEN); |
| 396 | const bool hddXfer = dev9.ata->dmaReady && (dev9.if_ctrl & SPD_IF_ATA_DMAEN); |
| 397 | |
| 398 | // Order operations based on iopWrite to ensure DMA has data/space to work with. |
| 399 | if (iopWrite) |
| 400 | { |
| 401 | // Perform DMA from IOP. |
| 402 | if (iopXfer) |
| 403 | IOPWriteFIFO(); |
| 404 | |
| 405 | // Drain the FIFO |
| 406 | if (hddXfer && !hddRead) |
| 407 | { |
| 408 | HDDReadFIFO(); |
| 409 | } |
| 410 | } |
| 411 | else |
| 412 | { |
| 413 | // Ensure FIFO has data. |
| 414 | if (hddXfer && hddRead) |
| 415 | { |
| 416 | HDDWriteFIFO(); |
| 417 | } |
| 418 | |
| 419 | if (iopXfer) |
| 420 | { |
| 421 | // Perform DMA to IOP. |
| 422 | IOPReadFIFO(); |
| 423 | |
| 424 | // Refill FIFO after DMA. |
| 425 | // Need to recheck dmaReady incase prior |
| 426 | // HDDWriteFIFO competed the transfer from HDD |
| 427 | if (hddXfer && hddRead && dev9.ata->dmaReady) |
| 428 | { |
| 429 | HDDWriteFIFO(); |
| 430 | } |
| 431 | } |
| 432 | } |
| 433 | |
| 434 | FIFOIntr(); |
| 435 | } |
| 436 | |
| 437 | u16 SpeedRead(u32 addr, int width) |
| 438 | { |
no test coverage detected