| 349 | Console.Error("DEV9: OVERFLOW BY IOP"); |
| 350 | } |
| 351 | void FIFOIntr() |
| 352 | { |
| 353 | //FIFO Buffer Full/Empty |
| 354 | const int unread = (dev9.fifo_bytes_write - dev9.fifo_bytes_read); |
| 355 | |
| 356 | if (unread == 0) |
| 357 | { |
| 358 | dev9.irqcause &= ~SPD_INTR_ATA_FIFO_DATA; |
| 359 | if ((dev9.irqcause & SPD_INTR_ATA_FIFO_EMPTY) == 0) |
| 360 | _DEV9irq(SPD_INTR_ATA_FIFO_EMPTY, 1); |
| 361 | } |
| 362 | else |
| 363 | { |
| 364 | dev9.irqcause &= ~SPD_INTR_ATA_FIFO_EMPTY; |
| 365 | if ((dev9.irqcause & SPD_INTR_ATA_FIFO_DATA) == 0) |
| 366 | _DEV9irq(SPD_INTR_ATA_FIFO_DATA, 1); |
| 367 | } |
| 368 | |
| 369 | if (unread == SPD_DBUF_AVAIL_MAX * 512) |
| 370 | { |
| 371 | if ((dev9.irqcause & SPD_INTR_ATA_FIFO_FULL) == 0) |
| 372 | _DEV9irq(SPD_INTR_ATA_FIFO_FULL, 1); |
| 373 | } |
| 374 | else |
| 375 | { |
| 376 | dev9.irqcause &= ~SPD_INTR_ATA_FIFO_FULL; |
| 377 | } |
| 378 | |
| 379 | // is DMA finished |
| 380 | if ((dev9.dma_iop_ptr != nullptr) && |
| 381 | (dev9.dma_iop_transfered == dev9.dma_iop_size)) |
| 382 | { |
| 383 | dev9.dma_iop_ptr = nullptr; |
| 384 | psxDMA8Interrupt(); |
| 385 | } |
| 386 | } |
| 387 | |
| 388 | // FIFO counters operate based on the direction set in SPD_R_XFR_CTRL |
| 389 | // Both might have to set to the same direction for (SPEED <-> HDD) to work |
no test coverage detected