Create an expression node for a 16-bit integer constant. */

Ditto the 'e' field of a modRM byte. */

Put to a specified lane of a Qreg. */

FIXME: duplicated in readdwarf3.c */

Clear the W bit on a REX byte, thereby changing the operand size back to whatever that instruction's default operand size is. */

Create a ternary expression */

XXX: make it faster ? */

Read word #0 of a gpr register. */

local helper */

Generate IR to get hold of the rounding mode bits in FPCR, and convert them to IR format. Bind the final result to the returned temp. */

Something bad happened. Cannot continue. */

Check the supplied *original* |atom| for undefinedness, and emit a complaint if so. Once that happens, mark it as defined. This is possible be

Read a 32-bit value from a guest floating-point register. */

Get from a specified lane of a Qreg. */

add a byte */

Emit an instruction ppc-endianly */

Make an int reg-reg move. */

(used for sanity checks only): check that both args are atoms and are identically-kinded. */

Handle a VEX_NDS_128_66_0F_WIG (3-addr) insn, with a simple IROp for the operation, no inversion of the left arg, and no swapping of args. */

Put value to accumulator(helper function for MIPS32 DSP ASE instructions). */

To be used to complain about hwcaps we cannot handle */

Plain ("low level") read from a reg; no +8 offset magic for r15. */

Lazy propagation of undefinedness from two values, resulting in the specified shadow type. */

Write the least significant nibble of src to the specified REG[FLD] (as per IBM/hardware notation). */

Read double word #0 of a fpr register containing DFP value. */

Write word #0 of a fpr to the guest state. */

All-lanes AVX256 binary operation: G[255:0] = V[255:0] `op` E[255:0] */

Encode the s390 rounding mode as it appears in the m3 field of certain instructions to VEX's IRRoundingMode. */