store vtop a register belonging to class 'rc'. lvalues are converted to values. Cannot be used if cannot be converted to register value (such as

Add a statement to the list held by irsb. */

AltiVec */

Get byte from register reg, byte pos from 0 to 3 (or 7 for MIPS64) . */

Read a 32-bit value from a guest integer register. */

Architected write to a VFP Freg. Handles conditional writes to the register: if guardT == IRTemp_INVALID then the write is unconditional. */

Write a floating point value and an integer into the flags thunk. The integer value is zero-extended first. */

Build IR to conditionally set the flags thunk. As with putIReg, if guard is IRTemp_INVALID then it's unconditional, else it holds a condition :

These are duplicated in guest_arm_toIR.c */

Handle a VEX_NDS_256_66_0F_WIG (3-addr) insn, with a simple IROp for the operation, no inversion of the left arg, and no swapping of args. */

Zero all except the least significant lane of |srcE|, where |size| indicates the lane size in the usual way. */

Allocates a 16-aligned block. Asserts if the allocation fails.

Put to the least significant lane of a Qreg. */

standard offset calculation, check prefix type */

Write word #0 of a gpr to the guest state. */

Send a message. 'message' should be positive.

Compute most significant bits of an address of type Addr. */

Compute a floating-point value into a register, the identity of which is returned. As with iselIntExpr_R, the register will be virtual and must not

Construct a non-virtual general purpose register */

Generate code to set APSR.GE[flagNo]. Each fn call sets 1 bit. flagNo: which flag bit to set [3...0] lowbits_to_ignore: 0 = look at all 32 bits

Sign extend an N-bit value up to 64 bits, by copying bit N-1 into all higher positions. */

Add a closure.

Return the message from the queue and pop it or return 0 if there are no messages.