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Functions22,271 in github.com/LouisBrunner/valgrind-macos

⨍ Functions 22,271◇ Types & classes 3,393
↓ 56 callersFunctionhaveF2no66noF3
Return True iff pfx has F2 set and 66 and F3 clear */
VEX/priv/guest_amd64_toIR.c:742
↓ 56 callersFunctioniregEnc
VEX/priv/host_ppc_defs.c:3377
↓ 56 callersFunctionmkNOT1
VEX/priv/guest_ppc_toIR.c:835
↓ 56 callersFunctionmkSizedOp
VEX/priv/guest_amd64_toIR.c:312
↓ 56 callersFunctionputDReg
VEX/priv/guest_mips_toIR.c:1962
↓ 56 callersFunctionputYMMRegLane128
VEX/priv/guest_amd64_toIR.c:1648
↓ 56 callersFunctionvregEnc3210
Produce a complete 4-bit integer register number. */
VEX/priv/host_amd64_defs.c:2213
↓ 55 callersFunctionmkIRExpr_HWord
VEX/priv/ir_defs.c:5469
↓ 55 callersFunctionmk_vMOVsd_RR
VEX/priv/host_amd64_isel.c:331
↓ 55 callersFunctionnewVRegF
VEX/priv/host_s390_isel.c:249
↓ 55 callersFunctionnewVRegI
VEX/priv/host_nanomips_isel.c:142
↓ 55 callersFunctionrealloc
memcheck/tests/freebsd/static_allocs.c:5
↓ 54 callersFunctionPPCInstr_FpLdSt
VEX/priv/host_ppc_defs.c:1087
↓ 54 callersFunctiongetFReg
Architected read from a VFP Freg. */
VEX/priv/guest_arm_toIR.c:885
↓ 54 callersFunctionhregAMD64_RSP
VEX/priv/host_amd64_defs.h:73
↓ 54 callersFunctionifieldOPClo10
Extract 10-bit secondary opcode, instr[10:1] */
VEX/priv/guest_ppc_toIR.c:369
↓ 54 callersFunctionmkU32
Create an expression to produce a 32-bit constant. */
VEX/priv/guest_riscv64_toIR.c:122
↓ 54 callersFunctionnewTemp
Generate a new temporary of the given type. */
VEX/priv/guest_riscv64_toIR.c:179
↓ 54 callersFunctionppHRegX86
VEX/priv/host_x86_defs.c:105
↓ 54 callersFunctionputQReg
Architected write to a Neon Qreg. Handles conditional writes to the register: if guardT == IRTemp_INVALID then the write is unconditional. */
VEX/priv/guest_arm_toIR.c:832
↓ 53 callersFunctiongen_op
generic gen_op: handles types problems */
perf/tinycc.c:11227
↓ 53 callersFunctionhregEncoding
VEX/priv/host_generic_regs.h:162
↓ 53 callersFunctionsub_from_sp
VEX/priv/host_ppc_isel.c:531
↓ 53 callersFunctionvex_bzero
Vectorised memset, copied from Valgrind's m_libcbase.c. */
VEX/priv/main_util.c:281
↓ 52 callersFunctionemulation_warning
VEX/priv/guest_s390_toIR.c:658
↓ 52 callersFunctionexpect
perf/tinycc.c:7102
↓ 52 callersFunctionfnptr_to_fnentry
Given a pointer to a function as obtained by "& functionname" in C, produce a pointer to the actual entry point for the function. For most platforms
VEX/priv/guest_ppc_toIR.c:254
↓ 52 callersFunctionfp_get_tag_ST
VEX/useful/hd_fpu.c:308
↓ 52 callersFunctionfp_is_empty_tag
VEX/useful/hd_fpu.c:293
↓ 52 callersFunctiongetIReg64
VEX/priv/guest_amd64_toIR.c:1109
↓ 52 callersFunctiongetXMMRegLane64
VEX/priv/guest_amd64_toIR.c:1557
↓ 52 callersFunctionput_ITSTATE
VEX/priv/guest_arm_toIR.c:962
↓ 52 callersFunctionset_aligned_word64_Origin_to_undef
memcheck/mc_main.c:2841
↓ 52 callersFunctiontry
none/tests/amd64/fxtract.c:21
↓ 52 callersFunctiontry
none/tests/x86/fxtract.c:20
↓ 51 callersFunctiongetAcc
Get value from accumulator (helper function for MIPS32 DSP ASE instructions). This function should be called before any other operation if widening
VEX/priv/guest_mips_toIR.c:1322
↓ 51 callersFunctionget_fpr_dw0
Read double word #0 of a fpr register. */
VEX/priv/guest_s390_toIR.c:1158
↓ 51 callersFunctiontriop
VEX/priv/mips_defs.h:105
↓ 51 callersFunctionwidenUto64
U-widen 1/8/16/32/64 bit int expr to 64. */
VEX/priv/guest_amd64_toIR.c:1819
↓ 51 callersFunctionxxprintf
none/tests/amd64/fb_test_amd64.c:364
↓ 50 callersFunctionIRExpr_Binop
VEX/priv/ir_defs.c:2426
↓ 50 callersFunctionadd_to_sp
VEX/priv/host_ppc_isel.c:523
↓ 50 callersFunctionemit_RXY
VEX/priv/host_s390_defs.c:1758
↓ 50 callersFunctionexec_op
VEX/test/test-amd64.h:105
↓ 50 callersFunctionexec_op
none/tests/amd64/fb_test_amd64.h:106
↓ 50 callersFunctioniselFltExpr
Nothing interesting here; really just wrappers for 64-bit stuff. */
VEX/priv/host_mips_isel.c:5908
↓ 50 callersFunctionmkSzImm
sz, ULong -> IRExpr */
VEX/priv/guest_ppc_toIR.c:1285
↓ 50 callersFunctionnewVRegI
VEX/priv/host_s390_isel.c:235
↓ 48 callersFunctionXXH_readLE64
coregrind/m_debuginfo/zstddeclib.c:10602
↓ 48 callersFunctionbreakupV256toV128s
VEX/priv/guest_amd64_toIR.c:9798
↓ 48 callersFunctiondis_SSEint_E_to_G
SSE integer binary operation: G = G `op` E (eLeft == False) G = E `op` G (eLeft == True) */
VEX/priv/guest_amd64_toIR.c:9271
↓ 48 callersFunctiongetDReg
Architected read from a VFP Dreg. */
VEX/priv/guest_arm_toIR.c:708
↓ 48 callersFunctionhregIndex
VEX/priv/host_generic_regs.h:157
↓ 48 callersFunctionsetFPUCondCode
VEX/priv/guest_mips_toIR.c:2011
↓ 48 callersFunctionszToITy
VEX/priv/guest_x86_toIR.c:430
↓ 48 callersFunctionvsx_matrix_ger
VEX/priv/guest_ppc_toIR.c:5670
↓ 47 callersFunctiondis_SSEint_E_to_G
SSE integer binary operation: G = G `op` E (eLeft == False) G = E `op` G (eLeft == True) */
VEX/priv/guest_x86_toIR.c:7253
↓ 47 callersFunctiondregEnc
VEX/priv/host_arm64_defs.c:2931
↓ 47 callersFunctionget_tok_str
XXX: buffer overflow */ XXX: float tokens */
perf/tinycc.c:7284
↓ 47 callersFunctionnameIRegE
VEX/priv/guest_amd64_toIR.c:1458
↓ 47 callersFunctionputIReg64
VEX/priv/guest_amd64_toIR.c:1115
↓ 46 callersFunctionIRExpr_GSPTR
VEX/priv/ir_defs.c:2483
↓ 46 callersFunctionX86RMI_Imm
VEX/priv/host_x86_defs.c:245
↓ 46 callersFunctionZSTD_isError
! ZSTD_isError() : * tells if a return value is an error code * symbol is required for external callers */
coregrind/m_debuginfo/zstddeclib.c:14909
↓ 46 callersFunctionprint
coregrind/m_ume/macho.c:81
↓ 46 callersFunctionput_fpr_dw0
Write double word #0 of a fpr to the guest state. */
VEX/priv/guest_s390_toIR.c:1149
↓ 46 callersFunctions390_sprintf
Helper function for writing out a V insn */
VEX/priv/host_s390_defs.c:6139
↓ 45 callersFunctiongetFReg64
Read a 64-bit value from a guest floating-point register. */
VEX/priv/guest_riscv64_toIR.c:505
↓ 45 callersFunctionmapReg
local helper */
VEX/priv/host_x86_defs.c:1514
↓ 45 callersFunctionmk_iMOVds_RR
VEX/priv/host_ppc_isel.c:513
↓ 45 callersFunctionputIReg64
Write a 64-bit value into a guest integer register. */
VEX/priv/guest_riscv64_toIR.c:387
↓ 45 callersFunctionvpushi
push integer constant */
perf/tinycc.c:10125
↓ 44 callersFunctionbind
VEX/priv/host_arm_isel.c:189
↓ 44 callersFunctionfp_get_reg_ST
VEX/useful/hd_fpu.c:365
↓ 44 callersFunctiongetIRegE
VEX/priv/guest_amd64_toIR.c:1416
↓ 44 callersFunctiongetQRegLO
Get from the least significant lane of a Qreg. */
VEX/priv/guest_arm64_toIR.c:1510
↓ 44 callersFunctionifieldBIT0
Extract lowest bit, instr[0] */
VEX/priv/guest_ppc_toIR.c:476
↓ 44 callersFunctionppIROp
VEX/priv/ir_defs.c:120
↓ 44 callersFunctionzmask_from_V128
none/tests/amd64/pcmpstr64.c:105
↓ 43 callersFunctionPPCInstr_Shft
VEX/priv/host_ppc_defs.c:844
↓ 43 callersFunctionerror
A few convenience utilities */
none/tests/s390x/disasm-test/main.c:399
↓ 43 callersFunctionfind_nsegment_idx
coregrind/m_aspacemgr/aspacemgr-linux.c:1391
↓ 43 callersFunctiongen_SIGNAL_if_not_16_aligned
VEX/priv/guest_amd64_toIR.c:10161
↓ 43 callersFunctionget_UChar
FIXME: document assumptions on endianness for get_UShort/UInt/ULong. */
coregrind/m_debuginfo/readdwarf3.c:241
↓ 43 callersFunctioniregEnc
VEX/priv/host_arm_defs.c:2780
↓ 43 callersFunctioniselVecExpr
VEX/priv/host_amd64_isel.c:3340
↓ 43 callersFunctionmk_iMOVds_RR
Make a int reg-reg move. */
VEX/priv/host_arm_isel.c:278
↓ 43 callersFunctionnoteTmpUsesIn
Helper for |preInstrumentationAnalysis|. */
memcheck/mc_translate.c:8588
↓ 43 callersFunctionputGST
VEX/priv/guest_ppc_toIR.c:3654
↓ 43 callersFunctions390_format_RSY
VEX/priv/guest_s390_toIR.c:2829
↓ 43 callersFunctionvswap
perf/tinycc.c:10217
↓ 42 callersFunctionPPCRH_Reg
VEX/priv/host_ppc_defs.c:329
↓ 42 callersFunctionX86Instr_Push
VEX/priv/host_x86_defs.c:637
↓ 42 callersFunctionemit_RRF2
VEX/priv/host_s390_defs.c:1633
↓ 42 callersFunctionget_fpr_w0
Read word #0 of a fpr register. */
VEX/priv/guest_s390_toIR.c:1135
↓ 42 callersFunctionisBogusAtom
memcheck/mc_translate.c:8337
↓ 42 callersFunctionis_NaN
SNAN: s = 1/0; exp all 1's; fraction is nonzero, with highest bit '1' * QNAN: s = 1/0; exp all 1's; fraction is nonzero, with highest bit '0' */
VEX/priv/guest_ppc_toIR.c:4368
↓ 42 callersFunctionllPutIReg
Plain ("low level") write to a reg; no jump or alignment magic for r15. */
VEX/priv/guest_arm_toIR.c:575
↓ 42 callersFunctionloadLE
VEX/priv/guest_arm_toIR.c:319
↓ 42 callersFunctionmkIRExprVec_3
VEX/priv/ir_defs.c:2515
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