Construct a non-virtual floating point register */

Architected write to a Neon Integer Dreg. Handles conditional writes to the register: if guardT == IRTemp_INVALID then the write is uncondition

Architected read from a Neon Qreg. */

A side exit that branches back to the insn immediately following the current insn if CONDITION is true. Does not set DisResult. */

Add a statement to the list held by "irbb". */

physical structure of mips instructions */ type I : opcode - 6 bits rs - 5 bits rt - 5 bits immediate -

* Convert LSB and MSB back into an address. * * @note It is assumed that sizeof(Addr) == sizeof(UWord). */

Calculates vr index according to instruction's rxb field and position of vr in instruction. Index of first argument must be 1 (not zero) */

FIXME: duplicated in readdwarf3.c */ Read a 'leb128' and advance *data accordingly. */

Create an expression to produce a 64-bit constant. */

Obtain ABI name of a register. */

Select insns for an integer-typed expression, and add them to the code list. Return a reg holding the result. This reg will be a virtual regis

Return True iff pfx has F3 set and 66 and F2 clear */

fs - fpu source register number. inst - fpu instruction that needs to be executed. sz32 - size of source register. opN - number of operads

(used for sanity checks only): is this an atom which looks like it's from original code? */

Local helper. */

Create a temporary of the given type and assign the expression to it */

Helper function for all vector operations */

Compute least significant bits of an address of type Addr. */

Encode the s390 rounding mode as it appears in the m3 field of certain instructions to VEX's IRRoundingMode. */

Doesn't assert if the relevant map_threads entry is NULL. */

local helper */