Create an expression node for a 32-bit integer constant. */

Write quadword of a vr to the guest state. */

Add a statement to the list held by "irbb". */

This generates a normal (non load-linked) load. */

Check a prefix doesn't have F2 or F3 set in it, since usually that completely changes what instruction it really is. */

Read a 64-bit value from a guest integer register. */

Add a statement that stores DATA at ADDR. This is a big-endian machine. */

Extract RA (1st source register) field, instr[20:16] */

Extract RD (destination register) field, instr[25:21] */

ws, wt - source MSA register numbers. inst - MSA fp instruction that needs to be executed. opN - number of operads: 1 - unary

Extract RB (2nd source register) field, instr[15:11] */

Add a statement to assign a value to a temporary. */

Extract primary opcode, instr[31:26] */

Little helper function for my sanity. ITE = if-then-else */

Get the (inverted, hence back to "normal") VEX.vvvv field. */

Add a statement to the current irsb. */

Add a statement to the list held by "irsb". */

Store a value to memory. If a value requires more than 8 bytes a series of 8-byte stores will be generated. */

local helper */

Generate a "standard 7" name, from bitQ and size. But also allow ".1d" since that's occasionally useful. */

Create an unary-operation expression. */

Load a value from memory. Loads of more than 8 byte are split into a series of 8-byte loads and combined using appropriate IROps. */

Emit an R-type instruction. */

|fullWidth| is a full V128 width result. Depending on bitQ, zero out the upper half. */

Write the low half of a YMM reg and zero out the upper half. */