Thumb16 and Thumb32 only. Returns true if reg is 13 or 15. Implements the BadReg predicate in the ARM ARM. */

Read a complete Qreg. */

... and extract the register number ... */

Use this to coerce the result of a C comparison to a Bool. This is useful when compiling with Intel icc with ultra-paranoid compilation flags (

Get contents of VSX guest register */

Ditto, but write to a reg instead. */

Ditto, but write to a reg instead. */

Create an expression that loads a TYPE sized value from ADDR. This is a big-endian machine. */

Architected read from a reg in ARM mode. This automagically adds 8 to all reads of r15. */

Add a statement to the list held by "irsb". */

Construct. The goal here is that compiler can fold this down to a constant in the case where the four arguments are constants, which is often t

Write double word #0 of a gpr to the guest state. */

Complain if first two args don't strcmp as equal. */

Read word #1 of a gpr register. */

Extract the 'g' field from a modRM byte. This only produces 3 bits, which is not a complete register number. You should avoid this function if

Read quadword of a vr register. */

and a handy shorthand for it */

return next token with macro substitution */

Ditto, but write to a VSX reg instead. */

Figure out whether the mod and rm parts of a modRM byte refer to a register or memory. If so, the byte will have the form 11XXXYYY, where YYY i

Convenience functions for atoms (IRExprs which are either Iex_Tmp or * Iex_Const). */

Write to a complete Qreg. */

Architected write to an integer register in Thumb mode. Writes to r15 are not allowed. Handles conditional writes to the register: if guardT =

Create an expression node for an 8-bit integer constant */

local helper */

Return the name of the given port or "UNKNOWN 0x1234" if not known.

Add a statement to the list held by "irbb". */

Create a binary-operation expression. */

Write word #1 of a gpr to the guest state. */

Architected write to an integer register in ARM mode. If it is to r15, record info so at the end of this insn's translation, a branch to it can

type R: opcode - 6 bits rs - 5 bits rt - 5 bits rd - 5 bits sa - 5 bits func - 6 bits */

Generates a random V128. Ensures that that it contains normalised FP numbers when viewed as either F16x8, F32x4 or F64x2, so that it is reasonable

Put value to DSPControl register. Expression e is written to DSPControl as is. If only certain bits of DSPControl need to be changed, it should be

Fetch a byte from the guest insn stream. */

Ditto, but write to a reg instead. */

(used for sanity checks only): is this an atom which looks like it's from shadow code? */

Return True iff pfx has 66, F2 and F3 clear */

Create an expression to read a temporary. */

This generates a normal (non store-conditional) store. */

Obtain ABI name of a register. */

Select insns for an integer-typed expression, and add them to the code list. Return a reg holding the result. This reg will be a virtual regis

Add a statement to the list held by "irsb". */

Architected read from a Neon Integer Dreg. */