| 1173 | } |
| 1174 | |
| 1175 | static void |
| 1176 | amd_thresholding_monitor(int i) |
| 1177 | { |
| 1178 | struct amd_et_state *cc; |
| 1179 | uint64_t misc; |
| 1180 | |
| 1181 | /* |
| 1182 | * Kludge: On 10h, banks after 4 are not thresholding but also may have |
| 1183 | * bogus Valid bits. Skip them. This is definitely fixed in 15h, but |
| 1184 | * I have not investigated whether it is fixed in earlier models. |
| 1185 | */ |
| 1186 | if (CPUID_TO_FAMILY(cpu_id) < 0x15 && i >= 5) |
| 1187 | return; |
| 1188 | |
| 1189 | /* The counter must be valid and present. */ |
| 1190 | misc = rdmsr(mca_msr_ops.misc(i)); |
| 1191 | if ((misc & (MC_MISC_AMD_VAL | MC_MISC_AMD_CNTP)) != |
| 1192 | (MC_MISC_AMD_VAL | MC_MISC_AMD_CNTP)) |
| 1193 | return; |
| 1194 | |
| 1195 | /* The register should not be locked. */ |
| 1196 | if ((misc & MC_MISC_AMD_LOCK) != 0) { |
| 1197 | if (bootverbose) |
| 1198 | printf("%s: 0x%jx: Bank %d: locked\n", __func__, |
| 1199 | (uintmax_t)misc, i); |
| 1200 | return; |
| 1201 | } |
| 1202 | |
| 1203 | /* |
| 1204 | * If counter is enabled then either the firmware or another CPU |
| 1205 | * has already claimed it. |
| 1206 | */ |
| 1207 | if ((misc & MC_MISC_AMD_CNTEN) != 0) { |
| 1208 | if (bootverbose) |
| 1209 | printf("%s: 0x%jx: Bank %d: already enabled\n", |
| 1210 | __func__, (uintmax_t)misc, i); |
| 1211 | return; |
| 1212 | } |
| 1213 | |
| 1214 | /* |
| 1215 | * Configure an Extended Interrupt LVT register for reporting |
| 1216 | * counter overflows if that feature is supported and the first |
| 1217 | * extended register is available. |
| 1218 | */ |
| 1219 | amd_elvt = lapic_enable_mca_elvt(); |
| 1220 | if (amd_elvt < 0) { |
| 1221 | printf("%s: Bank %d: lapic enable mca elvt failed: %d\n", |
| 1222 | __func__, i, amd_elvt); |
| 1223 | return; |
| 1224 | } |
| 1225 | |
| 1226 | /* Re-use Intel CMC support infrastructure. */ |
| 1227 | if (bootverbose) |
| 1228 | printf("%s: Starting AMD thresholding on bank %d\n", __func__, |
| 1229 | i); |
| 1230 | |
| 1231 | cc = &amd_et_state[PCPU_GET(cpuid)][i]; |
| 1232 | cc->cur_threshold = 1; |
no test coverage detected