* Initializes per-CPU machine check registers and enables corrected * machine check interrupts. */
| 1259 | * machine check interrupts. |
| 1260 | */ |
| 1261 | static void |
| 1262 | _mca_init(int boot) |
| 1263 | { |
| 1264 | uint64_t mcg_cap; |
| 1265 | uint64_t ctl, mask; |
| 1266 | int i, skip, family; |
| 1267 | |
| 1268 | family = CPUID_TO_FAMILY(cpu_id); |
| 1269 | |
| 1270 | /* MCE is required. */ |
| 1271 | if (!mca_enabled || !(cpu_feature & CPUID_MCE)) |
| 1272 | return; |
| 1273 | |
| 1274 | if (cpu_feature & CPUID_MCA) { |
| 1275 | if (boot) |
| 1276 | PCPU_SET(cmci_mask, 0); |
| 1277 | |
| 1278 | mcg_cap = rdmsr(MSR_MCG_CAP); |
| 1279 | if (mcg_cap & MCG_CAP_CTL_P) |
| 1280 | /* Enable MCA features. */ |
| 1281 | wrmsr(MSR_MCG_CTL, MCG_CTL_ENABLE); |
| 1282 | if (IS_BSP() && boot) |
| 1283 | mca_setup(mcg_cap); |
| 1284 | |
| 1285 | /* |
| 1286 | * Disable logging of level one TLB parity (L1TP) errors by |
| 1287 | * the data cache as an alternative workaround for AMD Family |
| 1288 | * 10h Erratum 383. Unlike the recommended workaround, there |
| 1289 | * is no performance penalty to this workaround. However, |
| 1290 | * L1TP errors will go unreported. |
| 1291 | */ |
| 1292 | if (cpu_vendor_id == CPU_VENDOR_AMD && family == 0x10 && |
| 1293 | !amd10h_L1TP) { |
| 1294 | mask = rdmsr(MSR_MC0_CTL_MASK); |
| 1295 | if ((mask & (1UL << 5)) == 0) |
| 1296 | wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5)); |
| 1297 | } |
| 1298 | if (amd_rascap & AMDRAS_SCALABLE_MCA) { |
| 1299 | mca_msr_ops.ctl = mca_smca_ctl_reg; |
| 1300 | mca_msr_ops.status = mca_smca_status_reg; |
| 1301 | mca_msr_ops.addr = mca_smca_addr_reg; |
| 1302 | mca_msr_ops.misc = mca_smca_misc_reg; |
| 1303 | } |
| 1304 | |
| 1305 | /* |
| 1306 | * The cmci_monitor() must not be executed |
| 1307 | * simultaneously by several CPUs. |
| 1308 | */ |
| 1309 | if (boot) |
| 1310 | mtx_lock_spin(&mca_lock); |
| 1311 | |
| 1312 | for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) { |
| 1313 | /* By default enable logging of all errors. */ |
| 1314 | ctl = 0xffffffffffffffffUL; |
| 1315 | skip = 0; |
| 1316 | |
| 1317 | if (cpu_vendor_id == CPU_VENDOR_INTEL) { |
| 1318 | /* |
no test coverage detected