| 207 | } |
| 208 | |
| 209 | static int |
| 210 | dmar_flush_for_ctx_entry(struct dmar_unit *dmar, bool force) |
| 211 | { |
| 212 | int error; |
| 213 | |
| 214 | /* |
| 215 | * If dmar declares Caching Mode as Set, follow 11.5 "Caching |
| 216 | * Mode Consideration" and do the (global) invalidation of the |
| 217 | * negative TLB entries. |
| 218 | */ |
| 219 | if ((dmar->hw_cap & DMAR_CAP_CM) == 0 && !force) |
| 220 | return (0); |
| 221 | if (dmar->qi_enabled) { |
| 222 | dmar_qi_invalidate_ctx_glob_locked(dmar); |
| 223 | if ((dmar->hw_ecap & DMAR_ECAP_DI) != 0 || force) |
| 224 | dmar_qi_invalidate_iotlb_glob_locked(dmar); |
| 225 | return (0); |
| 226 | } |
| 227 | error = dmar_inv_ctx_glob(dmar); |
| 228 | if (error == 0 && ((dmar->hw_ecap & DMAR_ECAP_DI) != 0 || force)) |
| 229 | error = dmar_inv_iotlb_glob(dmar); |
| 230 | return (error); |
| 231 | } |
| 232 | |
| 233 | static int |
| 234 | domain_init_rmrr(struct dmar_domain *domain, device_t dev, int bus, |
no test coverage detected