* Globally invalidate the IOTLB, busily waiting for the completion. */
| 451 | * Globally invalidate the IOTLB, busily waiting for the completion. |
| 452 | */ |
| 453 | int |
| 454 | dmar_inv_iotlb_glob(struct dmar_unit *unit) |
| 455 | { |
| 456 | int error, reg; |
| 457 | |
| 458 | DMAR_ASSERT_LOCKED(unit); |
| 459 | KASSERT(!unit->qi_enabled, ("QI enabled")); |
| 460 | |
| 461 | reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap); |
| 462 | /* See a comment about DMAR_CCMD_ICC in dmar_inv_ctx_glob. */ |
| 463 | dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT | |
| 464 | DMAR_IOTLB_IIRG_GLB | DMAR_IOTLB_DR | DMAR_IOTLB_DW); |
| 465 | DMAR_WAIT_UNTIL(((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) & |
| 466 | DMAR_IOTLB_IVT32) == 0)); |
| 467 | return (error); |
| 468 | } |
| 469 | |
| 470 | /* |
| 471 | * Flush the chipset write buffers. See 11.1 "Write Buffer Flushing" |
no test coverage detected